On 11/27/23 04:30, Andrew Stubbs wrote:
I tried this patch for AMD GCN. We have a similar problem with excess
extends, but also for vector modes. Each lane has a minimum 32 bits and
GCC's normal assumption is that vector registers have precisely the
number of bits they need, so the amdgcn backend patterns have explicit
sign/zero extends for QImode and HImode for the instructions that might
need it. It would be cool if this pass could eliminate some of those,
but at this point I just wanted to check it didn't break anything.
Unfortunately I get a crash building libgcc:
I strongly suspect this is the same thing that was originally reported
by Xi Ruoyao. Just getting back on top of things after the holiday.
I'll get the V2 posted today.
Jeff
