ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/
ISA documents are at https://developer.arm.com/documentation/ddi0487/latest/
gcc/ChangeLog:
* config/arm/arm_neon.h
(vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
(vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
(vst1q_f16_x4, vst1q_f32_x4): New.
(vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
(vst1q_bf16_x4): New.
* config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
* config/arm/neon.md (neon_vst1q_x4<mode>): New.
gcc/testsuite/ChangeLog:
* gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests.
* gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests.
---
gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++
gcc/config/arm/arm_neon_builtins.def | 1 +
gcc/config/arm/neon.md | 26 ++++
.../gcc.target/arm/simd/vst1q_base_xN_1.c | 59 +++++++++
.../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 8 +-
.../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 6 +
.../gcc.target/arm/simd/vst1q_p64_xN_1.c | 6 +
7 files changed, 219 insertions(+), 1 deletion(-)
diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h
index 46ee888410f..df3e23b6e95 100644
--- a/gcc/config/arm/arm_neon.h
+++ b/gcc/config/arm/arm_neon.h
@@ -11391,6 +11391,38 @@ vst1q_s64_x3 (int64_t * __a, int64x2x3_t __b)
__builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s8_x4 (int8_t * __a, int8x16x4_t __b)
+{
+ union { int8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s16_x4 (int16_t * __a, int16x8x4_t __b)
+{
+ union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s32_x4 (int32_t * __a, int32x4x4_t __b)
+{
+ union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v4si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_s64_x4 (int64_t * __a, int64x2x4_t __b)
+{
+ union { int64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_s8_x3 (int8_t * __a, int8x8x3_t __b)
@@ -11736,6 +11768,14 @@ vst1q_p64_x3 (poly64_t * __a, poly64x2x3_t __b)
__builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p64_x4 (poly64_t * __a, poly64x2x4_t __b)
+{
+ union { poly64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
#pragma GCC pop_options
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
@@ -11817,6 +11857,24 @@ vst1q_f32_x3 (float32_t * __a, float32x4x3_t __b)
__builtin_neon_vst1q_x3v4sf (__a, __bu.__o);
}
+#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE)
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f16_x4 (float16_t * __a, float16x8x4_t __b)
+{
+ union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8hf (__a, __bu.__o);
+}
+#endif
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_f32_x4 (float32_t * __a, float32x4x4_t __b)
+{
+ union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v4sf (__a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_u8 (uint8_t * __a, uint8x16_t __b)
@@ -11909,6 +11967,38 @@ vst1q_u64_x3 (uint64_t * __a, uint64x2x3_t __b)
__builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u8_x4 (uint8_t * __a, uint8x16x4_t __b)
+{
+ union { uint8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u16_x4 (uint16_t * __a, uint16x8x4_t __b)
+{
+ union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u32_x4 (uint32_t * __a, uint32x4x4_t __b)
+{
+ union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v4si ((__builtin_neon_si *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_u64_x4 (uint64_t * __a, uint64x2x4_t __b)
+{
+ union { uint64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1q_p8 (poly8_t * __a, poly8x16_t __b)
@@ -11955,6 +12045,22 @@ vst1q_p16_x3 (poly16_t * __a, poly16x8x3_t __b)
__builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p8_x4 (poly8_t * __a, poly8x16x4_t __b)
+{
+ union { poly8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o);
+}
+
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_p16_x4 (poly16_t * __a, poly16x8x4_t __b)
+{
+ union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c)
@@ -20647,6 +20753,14 @@ vst1q_bf16_x3 (bfloat16_t * __a, bfloat16x8x3_t __b)
__builtin_neon_vst1q_x3v8bf (__a, __bu.__o);
}
+__extension__ extern __inline void
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vst1q_bf16_x4 (bfloat16_t * __a, bfloat16x8x4_t __b)
+{
+ union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b };
+ __builtin_neon_vst1q_x4v8bf (__a, __bu.__o);
+}
+
__extension__ extern __inline void
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val)
diff --git a/gcc/config/arm/arm_neon_builtins.def
b/gcc/config/arm/arm_neon_builtins.def
index b1886372a1f..12f78800588 100644
--- a/gcc/config/arm/arm_neon_builtins.def
+++ b/gcc/config/arm/arm_neon_builtins.def
@@ -313,6 +313,7 @@ VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf,
v4sf, v8bf)
VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
VAR7 (STORE1, vst1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf)
+VAR7 (STORE1, vst1q_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf)
VAR14 (STORE1, vst1,
v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di,
v4bf, v8bf)
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index b69ed24c018..2fa4f85b820 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -5169,6 +5169,32 @@ if (BYTES_BIG_ENDIAN)
[(set_attr "type" "neon_store1_3reg<q>")]
)
+(define_insn "neon_vst1q_x4<mode>"
+ [(set (match_operand:XI 0 "neon_struct_operand" "=Um")
+ (unspec:XI [(match_operand:XI 1 "s_register_operand" "w")
+ (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
+ UNSPEC_VST1))]
+ "TARGET_NEON"
+{
+ int regno = REGNO (operands[1]);
+ rtx ops[5];
+ ops[0] = operands[0];
+ ops[1] = gen_rtx_REG (DImode, regno);
+ ops[2] = gen_rtx_REG (DImode, regno + 2);
+ ops[3] = gen_rtx_REG (DImode, regno + 4);
+ ops[4] = gen_rtx_REG (DImode, regno + 6);
+ output_asm_insn ("vst1.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
+
+ ops[1] = gen_rtx_REG (DImode, regno + 8);
+ ops[2] = gen_rtx_REG (DImode, regno + 10);
+ ops[3] = gen_rtx_REG (DImode, regno + 12);
+ ops[4] = gen_rtx_REG (DImode, regno + 14);
+ output_asm_insn ("vst1.<V_sz_elem>\t{%P1, %P2, %P3, %P4}, %A0", ops);
+ return "";
+}
+ [(set_attr "type" "neon_store1_4reg<q>")]
+)
+
(define_insn "neon_vst1_x4<mode>"
[(set (match_operand:OI 0 "neon_struct_operand" "=Um")
(unspec:OI [(match_operand:OI 1 "s_register_operand" "w")
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
index ba30fda514f..461aae3af62 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c
@@ -116,15 +116,74 @@ void test_vst1q_p16_x3 (poly16_t * ptr, poly16x8x3_t val)
vst1q_p16_x3 (ptr, val);
}
+void test_vst1q_u8_x4 (uint8_t * ptr, uint8x16x4_t val)
+{
+ vst1q_u8_x4 (ptr, val);
+}
+
+void test_vst1q_u16_x4 (uint16_t * ptr, uint16x8x4_t val)
+{
+ vst1q_u16_x4 (ptr, val);
+}
+
+void test_vst1q_u32_x4 (uint32_t * ptr, uint32x4x4_t val)
+{
+ vst1q_u32_x4 (ptr, val);
+}
+
+void test_vst1q_u64_x4 (uint64_t * ptr, uint64x2x4_t val)
+{
+ vst1q_u64_x4 (ptr, val);
+}
+
+void test_vst1q_s8_x4 (int8_t * ptr, int8x16x4_t val)
+{
+ vst1q_s8_x4 (ptr, val);
+}
+
+void test_vst1q_s16_x4 (int16_t * ptr, int16x8x4_t val)
+{
+ vst1q_s16_x4 (ptr, val);
+}
+
+void test_vst1q_s32_x4 (int32_t * ptr, int32x4x4_t val)
+{
+ vst1q_s32_x4 (ptr, val);
+}
+
+void test_vst1q_s64_x4 (int64_t * ptr, int64x2x4_t val)
+{
+ vst1q_s64_x4 (ptr, val);
+}
+
+void test_vst1q_f32_x4 (float32_t * ptr, float32x4x4_t val)
+{
+ vst1q_f32_x4 (ptr, val);
+}
+
+void test_vst1q_p8_x4 (poly8_t * ptr, poly8x16x4_t val)
+{
+ vst1q_p8_x4 (ptr, val);
+}
+
+void test_vst1q_p16_x4 (poly16_t * ptr, poly16x8x4_t val)
+{
+ vst1q_p16_x4 (ptr, val);
+}
+
/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+\},
\[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+,
d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\},
\[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+,
d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */
/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+\},
\[r[0-9]+\]\n} 6 } } */
+/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+,
d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */
/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\},
\[r[0-9]+:64\]\n} 4 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+,
d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
index 2593c31c756..84fa8509db8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c
@@ -15,5 +15,11 @@ void test_vst1q_bf16_x3 (bfloat16_t * ptr, bfloat16x8x3_t
val)
vst1q_bf16_x3 (ptr, val);
}
+void test_vst1q_bf16_x4 (bfloat16_t * ptr, bfloat16x8x4_t val)
+{
+ vst1q_bf16_x4 (ptr, val);
+}
+
/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\},
\[r[0-9]+\]\n} 1 } } */
-/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\},
\[r[0-9]+\]\n} 2 } } */
\ No newline at end of file
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\},
\[r[0-9]+\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+,
d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
index 28e949b557a..5b13edf9998 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c
@@ -15,5 +15,11 @@ void test_vst1q_f16_x3 (float16_t * ptr, float16x8x3_t val)
vst1q_f16_x3 (ptr, val);
}
+void test_vst1q_f16_x4 (float16_t * ptr, float16x8x4_t val)
+{
+ vst1q_f16_x4 (ptr, val);
+}
+
/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\},
\[r[0-9]+\]\n} 1 } } */
/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\},
\[r[0-9]+\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+,
d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
index 7878d936b9f..f49917d5ec8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c
@@ -15,5 +15,11 @@ void test_vst1q_p64_x3 (poly64_t * ptr, poly64x2x3_t val)
vst1q_p64_x3 (ptr, val);
}
+void test_vst1q_p64_x4 (poly64_t * ptr, poly64x2x4_t val)
+{
+ vst1q_p64_x4 (ptr, val);
+}
+
/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\},
\[r[0-9]+:64\]\n} 1 } } */
/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\},
\[r[0-9]+:64\]\n} 2 } } */
+/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+,
d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */
