Hi Philipp,
Could you rebase this patch on top of master please.
Essentially we put each tuning model in its own file now.
Thanks,
Tamar
> -----Original Message-----
> From: Philipp Tomsich <philipp.toms...@vrull.eu>
> Sent: Thursday, November 16, 2023 6:16 AM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <kyrylo.tkac...@arm.com>; Philipp Tomsich
> <philipp.toms...@vrull.eu>
> Subject: [PATCH] aarch64: Add support for Ampere-1B (-mcpu=ampere1b)
> CPU
>
> This patch adds initial support for Ampere-1B core.
>
> The Ampere-1B core implements ARMv8.7 with the following (compiler
> visible) extensions:
> - CSSC (Common Short Sequence Compression instructions),
> - MTE (Memory Tagging Extension)
> - SM3/SM4
>
> gcc/ChangeLog:
>
> * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add ampere-
> 1b
> * config/aarch64/aarch64-cost-tables.h: Add ampere1b_extra_costs
> * config/aarch64/aarch64.cc: Add ampere1b_prefetch_tune and
> ampere1b_advsimd_vector_costs
> * config/aarch64/aarch64-tune.md: Regenerate
> * doc/invoke.texi: Document -mcpu=ampere1b
>
> Signed-off-by: Philipp Tomsich <philipp.toms...@vrull.eu>
> ---
>
> gcc/config/aarch64/aarch64-cores.def | 1 +
> gcc/config/aarch64/aarch64-cost-tables.h | 107
> +++++++++++++++++++++++
> gcc/config/aarch64/aarch64-tune.md | 2 +-
> gcc/config/aarch64/aarch64.cc | 89 +++++++++++++++++++
> gcc/doc/invoke.texi | 2 +-
> 5 files changed, 199 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/aarch64/aarch64-cores.def
> b/gcc/config/aarch64/aarch64-cores.def
> index eae40b29df6..19dfb133d29 100644
> --- a/gcc/config/aarch64/aarch64-cores.def
> +++ b/gcc/config/aarch64/aarch64-cores.def
> @@ -74,6 +74,7 @@ AARCH64_CORE("thunderxt83", thunderxt83,
> thunderx, V8A, (CRC, CRYPTO), thu
> /* Ampere Computing ('\xC0') cores. */
> AARCH64_CORE("ampere1", ampere1, cortexa57, V8_6A, (F16, RNG, AES,
> SHA3), ampere1, 0xC0, 0xac3, -1) AARCH64_CORE("ampere1a", ampere1a,
> cortexa57, V8_6A, (F16, RNG, AES, SHA3, SM4, MEMTAG), ampere1a, 0xC0,
> 0xac4, -1)
> +AARCH64_CORE("ampere1b", ampere1b, cortexa57, V8_7A, (F16, RNG,
> AES,
> +SHA3, SM4, MEMTAG, CSSC), ampere1b, 0xC0, 0xac5, -1)
> /* Do not swap around "emag" and "xgene1",
> this order is required to handle variant correctly. */
> AARCH64_CORE("emag", emag, xgene1, V8A, (CRC, CRYPTO), emag,
> 0x50, 0x000, 3)
> diff --git a/gcc/config/aarch64/aarch64-cost-tables.h
> b/gcc/config/aarch64/aarch64-cost-tables.h
> index 0cb638f3a13..4c8da7f119b 100644
> --- a/gcc/config/aarch64/aarch64-cost-tables.h
> +++ b/gcc/config/aarch64/aarch64-cost-tables.h
> @@ -882,4 +882,111 @@ const struct cpu_cost_table ampere1a_extra_costs
> =
> }
> };
>
> +const struct cpu_cost_table ampere1b_extra_costs = {
> + /* ALU */
> + {
> + 0, /* arith. */
> + 0, /* logical. */
> + 0, /* shift. */
> + COSTS_N_INSNS (1), /* shift_reg. */
> + 0, /* arith_shift. */
> + COSTS_N_INSNS (1), /* arith_shift_reg. */
> + 0, /* log_shift. */
> + COSTS_N_INSNS (1), /* log_shift_reg. */
> + 0, /* extend. */
> + COSTS_N_INSNS (1), /* extend_arith. */
> + 0, /* bfi. */
> + 0, /* bfx. */
> + 0, /* clz. */
> + 0, /* rev. */
> + 0, /* non_exec. */
> + true /* non_exec_costs_exec. */
> + },
> + {
> + /* MULT SImode */
> + {
> + COSTS_N_INSNS (2), /* simple. */
> + COSTS_N_INSNS (2), /* flag_setting. */
> + COSTS_N_INSNS (2), /* extend. */
> + COSTS_N_INSNS (3), /* add. */
> + COSTS_N_INSNS (3), /* extend_add. */
> + COSTS_N_INSNS (12) /* idiv. */
> + },
> + /* MULT DImode */
> + {
> + COSTS_N_INSNS (2), /* simple. */
> + 0, /* flag_setting (N/A). */
> + COSTS_N_INSNS (2), /* extend. */
> + COSTS_N_INSNS (3), /* add. */
> + COSTS_N_INSNS (3), /* extend_add. */
> + COSTS_N_INSNS (18) /* idiv. */
> + }
> + },
> + /* LD/ST */
> + {
> + COSTS_N_INSNS (2), /* load. */
> + COSTS_N_INSNS (2), /* load_sign_extend. */
> + 0, /* ldrd (n/a). */
> + 0, /* ldm_1st. */
> + 0, /* ldm_regs_per_insn_1st. */
> + 0, /* ldm_regs_per_insn_subsequent. */
> + COSTS_N_INSNS (3), /* loadf. */
> + COSTS_N_INSNS (3), /* loadd. */
> + COSTS_N_INSNS (3), /* load_unaligned. */
> + 0, /* store. */
> + 0, /* strd. */
> + 0, /* stm_1st. */
> + 0, /* stm_regs_per_insn_1st. */
> + 0, /* stm_regs_per_insn_subsequent. */
> + COSTS_N_INSNS (1), /* storef. */
> + COSTS_N_INSNS (1), /* stored. */
> + COSTS_N_INSNS (1), /* store_unaligned. */
> + COSTS_N_INSNS (3), /* loadv. */
> + COSTS_N_INSNS (3) /* storev. */
> + },
> + {
> + /* FP SFmode */
> + {
> + COSTS_N_INSNS (18), /* div. */
> + COSTS_N_INSNS (3), /* mult. */
> + COSTS_N_INSNS (3), /* mult_addsub. */
> + COSTS_N_INSNS (3), /* fma. */
> + COSTS_N_INSNS (2), /* addsub. */
> + COSTS_N_INSNS (1), /* fpconst. */
> + COSTS_N_INSNS (2), /* neg. */
> + COSTS_N_INSNS (2), /* compare. */
> + COSTS_N_INSNS (2), /* widen. */
> + COSTS_N_INSNS (2), /* narrow. */
> + COSTS_N_INSNS (6), /* toint. */
> + COSTS_N_INSNS (4), /* fromint. */
> + COSTS_N_INSNS (2) /* roundint. */
> + },
> + /* FP DFmode */
> + {
> + COSTS_N_INSNS (18), /* div. */
> + COSTS_N_INSNS (3), /* mult. */
> + COSTS_N_INSNS (3), /* mult_addsub. */
> + COSTS_N_INSNS (3), /* fma. */
> + COSTS_N_INSNS (2), /* addsub. */
> + COSTS_N_INSNS (1), /* fpconst. */
> + COSTS_N_INSNS (2), /* neg. */
> + COSTS_N_INSNS (2), /* compare. */
> + COSTS_N_INSNS (2), /* widen. */
> + COSTS_N_INSNS (2), /* narrow. */
> + COSTS_N_INSNS (6), /* toint. */
> + COSTS_N_INSNS (4), /* fromint. */
> + COSTS_N_INSNS (2) /* roundint. */
> + }
> + },
> + /* Vector */
> + {
> + COSTS_N_INSNS (1), /* alu. */
> + COSTS_N_INSNS (2), /* mult. */
> + COSTS_N_INSNS (1), /* movi. */
> + COSTS_N_INSNS (1), /* dup. */
> + COSTS_N_INSNS (1) /* extract. */
> + }
> +};
> +
> #endif
> diff --git a/gcc/config/aarch64/aarch64-tune.md
> b/gcc/config/aarch64/aarch64-tune.md
> index c969277d617..737be6da71b 100644
> --- a/gcc/config/aarch64/aarch64-tune.md
> +++ b/gcc/config/aarch64/aarch64-tune.md
> @@ -1,5 +1,5 @@
> ;; -*- buffer-read-only: t -*-
> ;; Generated automatically by gentune.sh from aarch64-cores.def
> (define_attr "tune"
> -
> "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunder
> xt81,thunderxt83,ampere1,ampere1a,emag,xgene1,falkor,qdf24xx,exynosm1
> ,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa7
> 6,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortexa65,cortex
> a65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,octeontx2t
> 98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octeontx2f95m
> m,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,saphira,cor
> texa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa5
> 3,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,cortexa520,
> cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neoversen2,n
> eoversev2,demeter"
> +
> "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thun
> derx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunder
> xt81,thunderxt83,ampere1,ampere1a,ampere1b,emag,xgene1,falkor,qdf24xx
> ,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa7
> 5,cortexa76,cortexa76ae,cortexa77,cortexa78,cortexa78ae,cortexa78c,cortex
> a65,cortexa65ae,cortexx1,cortexx1c,neoversen1,ares,neoversee1,octeontx2,
> octeontx2t98,octeontx2t96,octeontx2t93,octeontx2f95,octeontx2f95n,octe
> ontx2f95mm,a64fx,tsv110,thunderx3t110,neoversev1,zeus,neoverse512tvb,
> saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa
> 73cortexa53,cortexa75cortexa55,cortexa76cortexa55,cortexr82,cortexa510,c
> ortexa520,cortexa710,cortexa715,cortexa720,cortexx2,cortexx3,cortexx4,neo
> versen2,neoversev2,demeter"
> (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git
> a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index
> d89c94519e9..ffcf7ed65b8 100644
> --- a/gcc/config/aarch64/aarch64.cc
> +++ b/gcc/config/aarch64/aarch64.cc
> @@ -2013,6 +2013,95 @@ static const struct tune_params
> ampere1a_tunings =
> AARCH64_LDP_STP_POLICY_ALIGNED /* stp_policy_model. */
> };
>
> +static const cpu_prefetch_tune ampere1b_prefetch_tune = {
> + 48, /* num_slots */
> + 64, /* l1_cache_size */
> + 64, /* l1_cache_line_size */
> + 2048, /* l2_cache_size */
> + true, /* prefetch_dynamic_strides */
> + -1, /* minimum_stride */
> + -1 /* default_opt_level */
> +};
> +
> +static const advsimd_vec_cost ampere1b_advsimd_vector_cost = {
> + 1, /* int_stmt_cost */
> + 3, /* fp_stmt_cost */
> + 0, /* ld2_st2_permute_cost */
> + 0, /* ld3_st3_permute_cost */
> + 0, /* ld4_st4_permute_cost */
> + 2, /* permute_cost */
> + 8, /* reduc_i8_cost */
> + 6, /* reduc_i16_cost */
> + 4, /* reduc_i32_cost */
> + 2, /* reduc_i64_cost */
> + 9, /* reduc_f16_cost */
> + 6, /* reduc_f32_cost */
> + 3, /* reduc_f64_cost */
> + 5, /* store_elt_extra_cost */
> + 5, /* vec_to_scalar_cost */
> + 5, /* scalar_to_vec_cost */
> + 4, /* align_load_cost */
> + 4, /* unalign_load_cost */
> + 1, /* unalign_store_cost */
> + 1 /* store_cost */
> +};
> +
> +/* Ampere-1B costs for vector insn classes. */ static const struct
> +cpu_vector_cost ampere1b_vector_cost = {
> + 1, /* scalar_int_stmt_cost */
> + 3, /* scalar_fp_stmt_cost */
> + 4, /* scalar_load_cost */
> + 1, /* scalar_store_cost */
> + 1, /* cond_taken_branch_cost */
> + 1, /* cond_not_taken_branch_cost */
> + &ere1b_advsimd_vector_cost, /* advsimd */
> + nullptr, /* sve */
> + nullptr /* issue_info */
> +};
> +
> +static const struct tune_params ampere1b_tunings = {
> + &ere1b_extra_costs,
> + &generic_addrcost_table,
> + &generic_regmove_cost,
> + &ere1b_vector_cost,
> + &generic_branch_cost,
> + &generic_approx_modes,
> + SVE_NOT_IMPLEMENTED, /* sve_width */
> + { 3, /* load_int. */
> + 1, /* store_int. */
> + 4, /* load_fp. */
> + 4, /* store_fp. */
> + 4, /* load_pred. */
> + 4 /* store_pred. */
> + }, /* memmov_cost. */
> + 4, /* issue_rate */
> + (AARCH64_FUSE_ADRP_ADD | AARCH64_FUSE_AES_AESMC |
> + AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_MOVK_MOVK |
> + AARCH64_FUSE_ALU_BRANCH /* adds, ands, bics, ccmp, ccmn */ |
> + AARCH64_FUSE_CMP_BRANCH | AARCH64_FUSE_ALU_CBZ |
> + AARCH64_FUSE_ADDSUB_2REG_CONST1),
> + /* fusible_ops */
> + "32", /* function_align. */
> + "4", /* jump_align. */
> + "32:16", /* loop_align. */
> + 2, /* int_reassoc_width. */
> + 4, /* fp_reassoc_width. */
> + 1, /* fma_reassoc_width. */
> + 2, /* vec_reassoc_width. */
> + 2, /* min_div_recip_mul_sf. */
> + 2, /* min_div_recip_mul_df. */
> + 0, /* max_case_values. */
> + tune_params::AUTOPREFETCHER_STRONG, /* autoprefetcher_model. */
> + (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND), /* tune_flags. */
> + &ere1b_prefetch_tune,
> + AARCH64_LDP_STP_POLICY_ALIGNED, /* ldp_policy_model. */
> + AARCH64_LDP_STP_POLICY_ALIGNED /* stp_policy_model. */
> +};
> +
> static const advsimd_vec_cost neoversev1_advsimd_vector_cost = {
> 2, /* int_stmt_cost */
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index
> 1748afdbfe0..58edb85039f 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -20755,7 +20755,7 @@ performance of the code. Permissible values for
> this option are:
> @samp{cortex-r82}, @samp{cortex-x1}, @samp{cortex-x1c}, @samp{cortex-
> x2}, @samp{cortex-x3}, @samp{cortex-x4}, @samp{cortex-a510},
> @samp{cortex-a520}, @samp{cortex-a710}, @samp{cortex-a715},
> @samp{cortex-a720}, @samp{ampere1}, -@samp{ampere1a}, and
> @samp{native}.
> +@samp{ampere1a}, @samp{ampere1b}, and @samp{native}.
>
> The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
> @samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53},
> --
> 2.34.1
