We have no FNE.fmt machine instructions, but we can emulate them for the
purpose of conditional-move and conditional-add operations by using the
respective FEQ.fmt instruction and then swapping the data input operands
or complementing the mask for the conditional addend respectively, so
update our handlers accordingly.
gcc/
* config/riscv/riscv-protos.h (riscv_expand_float_scc): Add
`invert_ptr' parameter.
* config/riscv/riscv.cc (riscv_emit_float_compare): Add NE
inversion handling.
(riscv_expand_float_scc): Pass `invert_ptr' through to
`riscv_emit_float_compare'.
(riscv_expand_conditional_move): Pass `&invert' to
`riscv_expand_float_scc'.
* config/riscv/riscv.md (add<mode>cc): Likewise.
---
gcc/config/riscv/riscv-protos.h | 3 ++-
gcc/config/riscv/riscv.cc | 23 +++++++++++++++--------
gcc/config/riscv/riscv.md | 2 +-
3 files changed, 18 insertions(+), 10 deletions(-)
gcc-riscv-emit-float-compare-ne.diff
Index: gcc/gcc/config/riscv/riscv-protos.h
===================================================================
--- gcc.orig/gcc/config/riscv/riscv-protos.h
+++ gcc/gcc/config/riscv/riscv-protos.h
@@ -132,7 +132,8 @@ riscv_zcmp_valid_stack_adj_bytes_p (HOST
#ifdef RTX_CODE
extern void riscv_expand_int_scc (rtx, enum rtx_code, rtx, rtx, bool
*invert_ptr = 0);
-extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx);
+extern void riscv_expand_float_scc (rtx, enum rtx_code, rtx, rtx,
+ bool *invert_ptr = nullptr);
extern void riscv_expand_conditional_branch (rtx, enum rtx_code, rtx, rtx);
extern rtx riscv_emit_unary (enum rtx_code code, rtx dest, rtx x);
extern rtx riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y);
Index: gcc/gcc/config/riscv/riscv.cc
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.cc
+++ gcc/gcc/config/riscv/riscv.cc
@@ -3965,7 +3965,8 @@ riscv_emit_int_compare (enum rtx_code *c
/* Like riscv_emit_int_compare, but for floating-point comparisons. */
static void
-riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1)
+riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1,
+ bool *invert_ptr = nullptr)
{
rtx tmp0, tmp1, cmp_op0 = *op0, cmp_op1 = *op1;
enum rtx_code fp_code = *code;
@@ -4029,10 +4030,15 @@ riscv_emit_float_compare (enum rtx_code
#undef UNORDERED_COMPARISON
case NE:
- *code = EQ;
- *op0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op1);
- *op1 = const0_rtx;
- break;
+ fp_code = EQ;
+ if (invert_ptr != nullptr)
+ *invert_ptr = !*invert_ptr;
+ else
+ {
+ cmp_op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1);
+ cmp_op1 = const0_rtx;
+ }
+ gcc_fallthrough ();
case EQ:
case LE:
@@ -4078,9 +4084,10 @@ riscv_expand_int_scc (rtx target, enum r
/* Like riscv_expand_int_scc, but for floating-point comparisons. */
void
-riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1)
+riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1,
+ bool *invert_ptr)
{
- riscv_emit_float_compare (&code, &op0, &op1);
+ riscv_emit_float_compare (&code, &op0, &op1, invert_ptr);
machine_mode mode = GET_MODE (target);
if (mode != word_mode)
@@ -4171,7 +4178,7 @@ riscv_expand_conditional_move (rtx dest,
riscv_expand_int_scc (tmp, code, op0, op1, invert_ptr);
else if (FLOAT_MODE_P (mode0)
&& fp_scc_comparison (op, GET_MODE (op)))
- riscv_expand_float_scc (tmp, code, op0, op1);
+ riscv_expand_float_scc (tmp, code, op0, op1, &invert);
else
return false;
Index: gcc/gcc/config/riscv/riscv.md
===================================================================
--- gcc.orig/gcc/config/riscv/riscv.md
+++ gcc/gcc/config/riscv/riscv.md
@@ -2697,7 +2697,7 @@
if (INTEGRAL_MODE_P (mode0))
riscv_expand_int_scc (reg0, code, cmp0, cmp1, &invert);
else if (FLOAT_MODE_P (mode0) && fp_scc_comparison (cmp, GET_MODE (cmp)))
- riscv_expand_float_scc (reg0, code, cmp0, cmp1);
+ riscv_expand_float_scc (reg0, code, cmp0, cmp1, &invert);
else
FAIL;
