Allow using -march=la664 and -mtune=la664. -march=la664 implies -mdiv32
and -mld-seq-sa. -mtune=la664 is currently same as -mtune=la464 and it
may need an update later.
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings: Add la664 as
STR_CPU_LA664.
* config/loongarch/genopts/loongarch.opt.in (cpu_type): Add
la664.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-str.h: Regenerate.
* config/loongarch/loongarch-def.h (CPU_LA664): Define.
(N_ARCH_TYPES): Increase to 5.
(N_TUNE_TYPES): Increase to 5.
* config/loongarch/loongarch-def.cc (loongarch_cpu_strings):
Set [CPU_LA664] to STR_CPU_LA664.
(loongarch_cpu_default_isa): Set [CPU_LA664] to
{ISA_BASE_LA64V100, ISA_EXT_FPU64, ISA_EXT_SIMD_LASX} with
OPTION_MASK_ISA_DIV32 and OPTION_MASK_ISA_LD_SEQ_SA implied.
(loongarch_cpu_cache): Set [CPU_LA664] to la464_cache ().
The CPUCFG fields about cache are same on LA464 and LA664.
(loongarch_cpu_align): Set [CPU_LA664] to la464_align ().
This may be inaccurate and need an update.
(loongarch_cpu_issue_rate): Set [CPU_LA664] to 4.
This may be inaccurate and need an update.
(loongarch_cpu_multipass_dfa_lookahead): Set [CPU_LA664] to 4.
This may be inaccurate and need an update.
* config/loongarch/loongarch-opts.h (TARGET_uARCH_LA464): Return
true for -mtune=la664 for now.
---
.../loongarch/genopts/loongarch-strings | 1 +
gcc/config/loongarch/genopts/loongarch.opt.in | 3 +++
gcc/config/loongarch/loongarch-def.cc | 26 ++++++++++++++-----
gcc/config/loongarch/loongarch-def.h | 5 ++--
gcc/config/loongarch/loongarch-opts.h | 6 +++--
gcc/config/loongarch/loongarch-str.h | 1 +
gcc/config/loongarch/loongarch.opt | 3 +++
7 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/gcc/config/loongarch/genopts/loongarch-strings
b/gcc/config/loongarch/genopts/loongarch-strings
index 8e412f7536e..7bc4824007e 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -26,6 +26,7 @@ STR_CPU_NATIVE native
STR_CPU_ABI_DEFAULT abi-default
STR_CPU_LOONGARCH64 loongarch64
STR_CPU_LA464 la464
+STR_CPU_LA664 la664
# Base architecture
STR_ISA_BASE_LA64V100 la64
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in
b/gcc/config/loongarch/genopts/loongarch.opt.in
index 4a22039681f..483b185b059 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -107,6 +107,9 @@ Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@)
Value(CPU_LOONGARCH64)
EnumValue
Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
+EnumValue
+Enum(cpu_type) String(@@STR_CPU_LA664@@) Value(CPU_LA664)
+
m@@OPTSTR_ARCH@@=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch)
Init(M_OPT_UNSET)
-m@@OPTSTR_ARCH@@=PROCESSOR Generate code for the given PROCESSOR ISA.
diff --git a/gcc/config/loongarch/loongarch-def.cc
b/gcc/config/loongarch/loongarch-def.cc
index 9c2ec1ec135..cf8b66e9130 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -21,6 +21,8 @@ along with GCC; see the file COPYING3. If not see
#define IN_TARGET_CODE
#include "config.h"
#include "system.h"
+#include "coretypes.h"
+#include "options.h"
#include "loongarch-def.h"
#include "loongarch-str.h"
@@ -38,7 +40,8 @@ array_tune<const char *> loongarch_cpu_strings =
array_tune<const char *> ()
.set (CPU_NATIVE, STR_CPU_NATIVE)
.set (CPU_ABI_DEFAULT, STR_CPU_ABI_DEFAULT)
.set (CPU_LOONGARCH64, STR_CPU_LOONGARCH64)
- .set (CPU_LA464, STR_CPU_LA464);
+ .set (CPU_LA464, STR_CPU_LA464)
+ .set (CPU_LA664, STR_CPU_LA664);
array_arch<loongarch_isa> loongarch_cpu_default_isa =
array_arch<loongarch_isa> ()
@@ -50,7 +53,14 @@ array_arch<loongarch_isa> loongarch_cpu_default_isa =
loongarch_isa ()
.base_ (ISA_BASE_LA64V100)
.fpu_ (ISA_EXT_FPU64)
- .simd_ (ISA_EXT_SIMD_LASX));
+ .simd_ (ISA_EXT_SIMD_LASX))
+ .set (CPU_LA664,
+ loongarch_isa ()
+ .base_ (ISA_BASE_LA64V100)
+ .fpu_ (ISA_EXT_FPU64)
+ .simd_ (ISA_EXT_SIMD_LASX)
+ .evol_add_feat (OPTION_MASK_ISA_DIV32)
+ .evol_add_feat (OPTION_MASK_ISA_LD_SEQ_SA));
static inline loongarch_cache la464_cache ()
{
@@ -64,7 +74,8 @@ static inline loongarch_cache la464_cache ()
array_tune<loongarch_cache> loongarch_cpu_cache =
array_tune<loongarch_cache> ()
.set (CPU_LOONGARCH64, la464_cache ())
- .set (CPU_LA464, la464_cache ());
+ .set (CPU_LA464, la464_cache ())
+ .set (CPU_LA664, la464_cache ()); /* not changed */
static inline loongarch_align la464_align ()
{
@@ -74,7 +85,8 @@ static inline loongarch_align la464_align ()
array_tune<loongarch_align> loongarch_cpu_align =
array_tune<loongarch_align> ()
.set (CPU_LOONGARCH64, la464_align ())
- .set (CPU_LA464, la464_align ());
+ .set (CPU_LA464, la464_align ())
+ .set (CPU_LA664, la464_align ());
#define COSTS_N_INSNS(N) ((N) * 4)
@@ -115,12 +127,14 @@ const loongarch_rtx_cost_data
loongarch_rtx_cost_optimize_size =
array_tune<int> loongarch_cpu_issue_rate = array_tune<int> ()
.set (CPU_NATIVE, 4)
.set (CPU_LOONGARCH64, 4)
- .set (CPU_LA464, 4);
+ .set (CPU_LA464, 4)
+ .set (CPU_LA664, 4);
array_tune<int> loongarch_cpu_multipass_dfa_lookahead = array_tune<int> ()
.set (CPU_NATIVE, 4)
.set (CPU_LOONGARCH64, 4)
- .set (CPU_LA464, 4);
+ .set (CPU_LA464, 4)
+ .set (CPU_LA664, 4);
/* Wiring string definitions from loongarch-str.h to global arrays
with standard index values from loongarch-opts.h, so we can
diff --git a/gcc/config/loongarch/loongarch-def.h
b/gcc/config/loongarch/loongarch-def.h
index e74036fda33..87a66d9ce30 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -156,8 +156,9 @@ struct loongarch_target
#define CPU_ABI_DEFAULT 1
#define CPU_LOONGARCH64 2
#define CPU_LA464 3
-#define N_ARCH_TYPES 4
-#define N_TUNE_TYPES 4
+#define CPU_LA664 4
+#define N_ARCH_TYPES 5
+#define N_TUNE_TYPES 5
/* parallel tables. */
extern loongarch_def_array<const char *, N_ARCH_TYPES>
diff --git a/gcc/config/loongarch/loongarch-opts.h
b/gcc/config/loongarch/loongarch-opts.h
index aa99e510282..9badecb7cb6 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -89,8 +89,10 @@ loongarch_update_gcc_opt_status (struct loongarch_target
*target,
#define ISA_HAS_LASX (la_target.isa.simd == ISA_EXT_SIMD_LASX)
-/* TARGET_ macros for use in *.md template conditionals */
-#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464)
+/* TARGET_ macros for use in *.md template conditionals.
+ For now treat LA664 in the same way as LA464. */
+#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464 || \
+ la_target.cpu_tune == CPU_LA664)
/* Note: optimize_size may vary across functions,
while -m[no]-memcpy imposes a global constraint. */
diff --git a/gcc/config/loongarch/loongarch-str.h
b/gcc/config/loongarch/loongarch-str.h
index 3fa2ed5fc49..d9f4cc53d4c 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -30,6 +30,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_CPU_ABI_DEFAULT "abi-default"
#define STR_CPU_LOONGARCH64 "loongarch64"
#define STR_CPU_LA464 "la464"
+#define STR_CPU_LA664 "la664"
#define STR_ISA_BASE_LA64V100 "la64"
diff --git a/gcc/config/loongarch/loongarch.opt
b/gcc/config/loongarch/loongarch.opt
index b17df1302f7..a8be307f92d 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -115,6 +115,9 @@ Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64)
EnumValue
Enum(cpu_type) String(la464) Value(CPU_LA464)
+EnumValue
+Enum(cpu_type) String(la664) Value(CPU_LA664)
+
march=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch)
Init(M_OPT_UNSET)
-march=PROCESSOR Generate code for the given PROCESSOR ISA.
--
2.42.1
