On Sun, May 20, 2012 at 11:57 AM, Uros Bizjak <ubiz...@gmail.com> wrote:
> On Sun, May 20, 2012 at 4:15 PM, H.J. Lu <hongjiu...@intel.com> wrote:
>
>> We should warn passing SSE vector argument without SSE enabled changes
>> the ABI for 64-bit. Tested on Linux/x86-64. OK to install?
>>
>> 2012-05-20 H.J. Lu <hongjiu...@intel.com>
>>
>> PR target/53425
>> * config/i386/i386.c (type_natural_mode): Warn passing SSE
>> vector argument without SSE enabled changes the ABI.
>>
>> gcc/testsuite/
>>
>> 2012-05-20 H.J. Lu <hongjiu...@intel.com>
>>
>> PR target/53425
>> * gcc.target/i386/pr53425.c: New file.
>>
>> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
>> index eca542c..a56847a 100644
>> --- a/gcc/config/i386/i386.c
>> +++ b/gcc/config/i386/i386.c
>> @@ -5828,7 +5833,22 @@ type_natural_mode (const_tree type, const
>> CUMULATIVE_ARGS *cum)
>> return TYPE_MODE (type);
>> }
>> else
>> - return mode;
>> + {
>
> No need for these outermost braces.
It is needed to avoid
/export/gnu/import/git/gcc/gcc/config/i386/i386.c: In function
\u2018type_natural_mode\u2019:
/export/gnu/import/git/gcc/gcc/config/i386/i386.c:5813:9: warning:
suggest explicit braces to avoid ambiguous \u2018else\u2019
[-Wparentheses]
> BTW: Can you please also add MMX warning for -mno-mmx to be consistent
> with 32bit targets?
64-bit passes 8-byte vector in SSE register, not MMX register.
I updated the patch to want 8-byte vector. Is this patch OK?
Thanks.
--
H.J.
----
gcc/
2012-05-20 H.J. Lu <hongjiu...@intel.com>
PR target/53425
* config/i386/i386.c (type_natural_mode): Warn passing SSE
vector argument without SSE enabled changes the ABI.
gcc/testsuite/
2012-05-20 H.J. Lu <hongjiu...@intel.com>
PR target/53425
* gcc.target/i386/pr53425-1.c: New file.
* gcc.target/i386/pr53425-2.c: Likewise.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index eca542c..3c0b81c 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -5828,7 +5828,22 @@ type_natural_mode (const_tree type, const
CUMULATIVE_ARGS *cum)
return TYPE_MODE (type);
}
else
- return mode;
+ {
+ if ((size == 8 || size == 16) && !TARGET_SSE)
+ {
+ static bool warnedsse;
+
+ if (cum
+ && !warnedsse
+ && cum->warn_sse)
+ {
+ warnedsse = true;
+ warning (0, "SSE vector argument without SSE "
+ "enabled changes the ABI");
+ }
+ }
+ return mode;
+ }
}
gcc_unreachable ();
diff --git a/gcc/testsuite/gcc.target/i386/pr53425-1.c
b/gcc/testsuite/gcc.target/i386/pr53425-1.c
new file mode 100644
index 0000000..2446c0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr53425-1.c
@@ -0,0 +1,14 @@
+/* PR target/53425 */
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mno-sse" } */
+
+typedef double __v2df __attribute__ ((__vector_size__ (16)));
+
+extern __v2df x;
+
+extern void bar (__v2df);
+void
+foo (void)
+{
+ bar (x); /* { dg-message "warning: SSE vector argument without SSE
enabled changes the ABI" } */
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr53425-2.c
b/gcc/testsuite/gcc.target/i386/pr53425-2.c
new file mode 100644
index 0000000..b89a5b1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr53425-2.c
@@ -0,0 +1,14 @@
+/* PR target/53425 */
+/* { dg-do compile { target { ! { ia32 } } } } */
+/* { dg-options "-O2 -mno-sse" } */
+
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+
+extern __v2sf x;
+
+extern void bar (__v2sf);
+void
+foo (void)
+{
+ bar (x); /* { dg-message "warning: SSE vector argument without SSE
enabled changes the ABI" } */
+}
