[PATCH v1] RISC-V: Remove unnecessary asm check for binop constraint

pan2 . li Sun, 22 Oct 2023 23:01:36 -0700

From: Pan Li <pan2...@intel.com>

The vsetvl asm check is unnecessary for the binop constraint. We
should be focus for constrait and leave the vsetvl test to the
vsetvl pass.


gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/binop_vv_constraint-1.c: Remove the
        vsetvl asm check from func body.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-1.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-10.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-11.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-12.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-129.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-13.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-130.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-131.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-133.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-134.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-135.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-14.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-15.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-153.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-154.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-155.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-158.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-16.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-17.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-171.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-172.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-173.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-174.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-18.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-19.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-2.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-20.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-21.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-22.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-23.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-24.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-25.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-26.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-27.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-28.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-29.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-3.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-30.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-31.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-32.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-33.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-34.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-35.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-36.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-37.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-38.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-39.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-4.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-40.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-41.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-42.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-43.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-44.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-5.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-6.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-7.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-8.c: Ditto.
        * gcc.target/riscv/rvv/base/binop_vx_constraint-9.c: Ditto.
        * gcc.target/riscv/rvv/base/shift_vx_constraint-1.c: Ditto.
        * gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c: Ditto.
        * gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c: Ditto.
        * gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c: Ditto.
        * gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c: Ditto.
        * gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c: Ditto.
        * gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c: Ditto.
        * gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c: Ditto.
        * gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c: Ditto.
        * gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c: Ditto.
        * gcc.target/riscv/rvv/base/unop_v_constraint-1.c: Ditto.
        * gcc.target/riscv/rvv/base/unop_v_constraint-2.c: Ditto.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 .../riscv/rvv/base/binop_vv_constraint-1.c    | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-1.c    | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-10.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-11.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-12.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-129.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-13.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-130.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-131.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-133.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-134.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-135.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-14.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-15.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-153.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-154.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-155.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-158.c  | 10 ++++----
 .../riscv/rvv/base/binop_vx_constraint-16.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-17.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-171.c  |  8 -------
 .../riscv/rvv/base/binop_vx_constraint-172.c  |  4 ----
 .../riscv/rvv/base/binop_vx_constraint-173.c  |  8 -------
 .../riscv/rvv/base/binop_vx_constraint-174.c  |  4 ----
 .../riscv/rvv/base/binop_vx_constraint-18.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-19.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-2.c    | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-20.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-21.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-22.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-23.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-24.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-25.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-26.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-27.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-28.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-29.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-3.c    | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-30.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-31.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-32.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-33.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-34.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-35.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-36.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-37.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-38.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-39.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-4.c    | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-40.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-41.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-42.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-43.c   | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-44.c   | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-5.c    | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-6.c    | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-7.c    | 20 ++++++++--------
 .../riscv/rvv/base/binop_vx_constraint-8.c    | 20 ----------------
 .../riscv/rvv/base/binop_vx_constraint-9.c    | 20 ++++++++--------
 .../riscv/rvv/base/shift_vx_constraint-1.c    | 19 +++++++--------
 .../riscv/rvv/base/ternop_vv_constraint-1.c   |  6 ++---
 .../riscv/rvv/base/ternop_vv_constraint-2.c   |  6 ++---
 .../riscv/rvv/base/ternop_vv_constraint-3.c   |  6 ++---
 .../riscv/rvv/base/ternop_vv_constraint-4.c   |  6 ++---
 .../riscv/rvv/base/ternop_vv_constraint-5.c   |  6 ++---
 .../riscv/rvv/base/ternop_vv_constraint-6.c   |  6 ++---
 .../riscv/rvv/base/ternop_vx_constraint-1.c   | 10 ++++----
 .../riscv/rvv/base/ternop_vx_constraint-8.c   | 10 ++++----
 .../riscv/rvv/base/ternop_vx_constraint-9.c   | 10 ++++----
 .../riscv/rvv/base/unop_v_constraint-1.c      | 20 ++++++++--------
 .../riscv/rvv/base/unop_v_constraint-2.c      | 24 +++++++++----------
 71 files changed, 404 insertions(+), 749 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c
index 3372ec1d230..4fc7f408291 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 **     vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
 **     vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-1.c
index 09e0e21925b..9a248bfa613 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-10.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-10.c
index faf5ffb47f1..c40d6765f27 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-10.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-11.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-11.c
index 54fe941f6ad..b9b09a8b67f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-11.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vand\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
index 8a18a1df535..634c12a4c0e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-12.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c
index db5dfe1fc3e..b99628bf12b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-129.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+** ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+** ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+** ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-13.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-13.c
index d844e1baf2f..4d8e641e1b7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-13.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c
index da6b02ddd2d..47c984b8a0b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-130.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+** ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+** ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+** ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+** ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c
index 16d35c8053d..b6e12b3a9c8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-131.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmseq\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c
index 2da8ab7c15e..f6d0d7fb31d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-133.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c
index a83fee48494..ff39b24e3e0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-134.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c
index 767987657b9..4852601cd1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-135.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-14.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-14.c
index 6779dfe859a..4c07a334611 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-14.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-15.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-15.c
index 611a86f2b15..82cc944ad31 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-15.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c
index a941bcd3181..a0f6c676d88 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-153.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -26,9 +26,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -51,9 +51,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmslt\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c
index ddbde574565..8e18d763504 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-154.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*-15
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c
index d22f3e4baa6..4b5e68118ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-155.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c
index d22f3e4baa6..4b5e68118ef 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-158.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
@@ -47,9 +47,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,t[au],m[au]
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmsge\.vi\tv[0-9]+,\s*v[0-9]+,\s*16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
index 0a7a1e88391..651d61001c1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-16.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
index eeea3517e01..d19a9fda235 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-17.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
index 6e8669ae59e..591a99e4e1c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-171.c
@@ -7,10 +7,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au]
-**  ...
-**     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
-**  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -41,10 +37,6 @@ void f1 (void * in, void *out, int64_t x, int n)
 /*
 ** f2:
 **  ...
-**     vsetivli\t[a-x0-9]+,\s*4,e64,m1,t[au],m[au]
-**  ...
-**     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
-**  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c
index 060c853a698..ae48b085084 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-172.c
@@ -7,8 +7,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,\s*4,e32,m1,tu,m[au]
-**  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -39,8 +37,6 @@ void f1 (void * in, void *out, int64_t x, int n)
 /*
 ** f2:
 **  ...
-**     vsetivli\tzero,\s*4,e32,m1,tu,m[au]
-**  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
index af9c45e942b..ca68cc5b618 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-173.c
@@ -7,10 +7,6 @@
 /*
 ** f1:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au]
-**  ...
-**     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
-**  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -41,10 +37,6 @@ void f1 (void * in, void *out, int64_t x, int vl)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*[a-x0-9]+,e64,m1,t[au],m[au]
-**  ...
-**     vsetvli\tzero,\s*[a-x0-9]+,e32,m1,tu,m[au]
-**  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c
index f2e5d40ceb7..c566db4dce7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-174.c
@@ -7,8 +7,6 @@
 /*
 ** f1:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*zero,e32,m1,tu,m[au]
-**  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1down\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -39,8 +37,6 @@ void f1 (void * in, void *out, int64_t x, int vl)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,\s*zero,e32,m1,tu,m[au]
-**  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **  ...
 **     vslide1up\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-18.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-18.c
index 328564fb029..db8960074e6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-18.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmul\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmul\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
index f4616b4c72b..16f431542d8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-19.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-2.c
index 2c02c35ef57..9c40181bf7c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-2.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-20.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-20.c
index 441573623ab..d5c1dcfed3b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-20.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmax\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmax\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
index c082f4059c3..347c846dcbb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-21.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-22.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-22.c
index b4813626fc1..28a1bc1569d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-22.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmin\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmin\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
index fd6fd6740ca..bc414440ba2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c
index d8ed5b186a4..eb74df5cd5e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vmaxu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vmaxu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
index 66891acc15a..ce3f3af9c3d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c
index b70a1360b3c..9b578cc7ac7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vminu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vminu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
index 6f068296e5a..4946f84b916 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-27.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-28.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-28.c
index a239a3380bc..b1ca4cb8505 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-28.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdiv\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdiv\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
index 9424a46457e..5f2eede0422 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-3.c
index 1da0cb6e5ae..21c1fc5a89a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-3.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c
index 272c0eab273..a9ac723a5a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
index 9424a46457e..5f2eede0422 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c
index 272c0eab273..a9ac723a5a2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vdivu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vdivu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
index 6f2bca4b58f..88fcba60345 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c
index 45015d77d2d..edb35c89b68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
index 6f2bca4b58f..88fcba60345 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c
index 45015d77d2d..edb35c89b68 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, uint32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, uint32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, uint32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, uint8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vremu\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, uint8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vremu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-37.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-37.c
index 34de4458198..10322b61790 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-37.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-37.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-38.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-38.c
index 1374becb847..45452fe4597 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-38.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-38.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-39.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-39.c
index 21b77b952e0..ff470b37471 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-39.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-39.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
index 297ed238477..87a16453fea 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-4.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
index 653f043e471..c0321cefb9a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-40.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-41.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-41.c
index 4ff352bd7af..7b6a1a853ba 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-41.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-41.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vrsub\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-42.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-42.c
index 975ebe709b9..42f7ba4d011 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-42.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-42.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-43.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-43.c
index 4f3e9066f16..555832986e5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-43.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-43.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vrsub\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
index d4dc4e0fe6c..ab0f13ba255 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-44.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vrsub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-5.c
index 29eab66774e..0600f985894 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-5.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vxor\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-6.c
index 67fd655ece2..dae7aaac2f8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-6.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
 **     vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-7.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-7.c
index 71a320a1619..8b80a7f5450 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-7.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
 **     vxor\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*15,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vi\tv[0-9]+,\s*v[0-9]+,\s*15
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
index 797abbd2cc0..9bf9ff59de7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-8.c
@@ -6,8 +6,6 @@
 /*
 ** f1:
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,ma
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -29,12 +27,8 @@ void f1 (void * in, void *out, int32_t x)
 /*
 ** f2:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
-**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -56,12 +50,8 @@ void f2 (void * in, void *out, int32_t x)
 /*
 ** f3:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e32,m1,tu,mu
-**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
@@ -85,8 +75,6 @@ void f3 (void * in, void *out, int32_t x)
 /*
 ** f4:
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,ma
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
@@ -108,12 +96,8 @@ void f4 (void * in, void *out, int8_t x)
 /*
 ** f5:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,ta,ma
-**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **  ...
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -135,12 +119,8 @@ void f5 (void * in, void *out, int8_t x)
 /*
 ** f6:
 **  ...
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
-**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **  ...
-**     vsetivli\tzero,4,e8,mf8,tu,mu
-**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vxor\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-9.c
index ce786e15244..e92fe0c2d86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-9.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out, int32_t x)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out, int8_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
 **     vand\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out, int8_t x)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vand\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
index e40e193220c..250e017cc86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/shift_vx_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsll\.vi\tv[0-9]+,\s*v[0-9]+,31
@@ -24,10 +24,9 @@ void f1 (void * in, void *out)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ...
-**     vsetivli\tzero,4,e32,m1,ta,ma
 **     ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -48,9 +47,9 @@ void f2 (void * in, void *out)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*17
@@ -71,7 +70,7 @@ void f3 (void * in, void *out)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -90,9 +89,9 @@ void f4 (void * in, void *out, size_t x)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsll\.vi\tv[0-9]+,\s*v[0-9]+,\s*5
 **     vsll\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*5,\s*v0.t
@@ -112,9 +111,9 @@ void f5 (void * in, void *out)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsll\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c
index 838776e5c50..7d0a44e4372 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c
index 54506c1c918..61345f081b1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-2.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c
index 5ff07da1146..100f12e1c24 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c
index c280d97824f..4dd09ae84b9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c
index 1f71aa867c2..02263b58cfd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c
index 2d2ed661434..db77dffba7b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -30,7 +30,7 @@ void f1 (void * in, void * in2, void *out)
 
 /*
 ** f2:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -55,7 +55,7 @@ void f2 (void * in, void * in2, void *out)
 
 /*
 ** f3:
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vlm\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c
index 90e120655d7..99083a479fb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void * in2, void *out, int32_t x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c
index 82e14734056..6d0cd29cd06 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, float x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void * in2, void *out, float x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c
index 1beed49d9ac..db86eaabf16 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void * in2, void *out, float x)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
@@ -47,9 +47,9 @@ void f2 (void * in, void * in2, void *out, float x)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vfnma[c-d][c-d]\.vf\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
index 1266784fd8f..64f4407d0b6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
@@ -24,9 +24,9 @@ void f1 (void * in, void *out)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
 **     vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
@@ -46,9 +46,9 @@ void f2 (void * in, void *out)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle32\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e8,mf8,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
@@ -88,9 +88,9 @@ void f4 (void * in, void *out)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
 **     vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
@@ -110,9 +110,9 @@ void f5 (void * in, void *out)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e8,mf8,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vneg\.v\tv[0-9]+,\s*v[0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c
index 19f9365b42b..3344d423525 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c
@@ -5,7 +5,7 @@
 
 /*
 ** f1:
-**     vsetivli\tzero,4,e32,m1,tu,ma
+**  ...
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
@@ -24,12 +24,12 @@ void f1 (void * in, void *out)
 
 /*
 ** f2:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,ta,ma
+**  ...
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
-**     vsetvli\tzero,zero,e64,m2,ta,ma
+**  ...
 **     vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
 **     vse64\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
@@ -46,9 +46,9 @@ void f2 (void * in, void *out)
 
 /*
 ** f3:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e32,m1,tu,mu
+**  ...
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle16\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
@@ -69,7 +69,7 @@ void f3 (void * in, void *out)
 
 /*
 ** f4:
-**     vsetivli\tzero,4,e16,mf4,tu,ma
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
@@ -88,12 +88,12 @@ void f4 (void * in, void *out)
 
 /*
 ** f5:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e16,mf4,ta,ma
+**  ...
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
-**     vsetvli\tzero,zero,e32,mf2,ta,ma
+**  ...
 **     vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t
 **     vse32.v\tv[0-9]+,0\([a-x0-9]+\)
 **     ret
@@ -110,9 +110,9 @@ void f5 (void * in, void *out)
 
 /*
 ** f6:
-**     vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma
+**  ...
 **     vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-**     vsetivli\tzero,4,e16,mf4,tu,mu
+**  ...
 **     vle8\.v\tv[0-9]+,0\([a-x0-9]+\)
 **     vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
 **     vsext\.vf2\tv[0-9]+,\s*v[0-9]+
-- 
2.34.1

[PATCH v1] RISC-V: Remove unnecessary asm check for binop constraint

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