From: Ezra Sitorus <ezra.sito...@arm.com> This patch is part of a series of patches implementing the _xN variants of the vld1 intrinsic for AArch32. This patch adds the _x2 variants of the vld1 intrinsic. Tests use xN so that the latter variants (_x3, _x4) could be added. The previous vld1_x2 has been updated to vld1q_x2 to take into account that it works with 4-word-length types. vld1_x2 is now only for 2-word-length types.
ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/ ISA documents are at https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New. (vld1_f16_x2, vld1_f32_x2): New. (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New. (vld1_bf16_x2): New. (vld1q_types_x2): Updated to use vld1q_x2 from arm_neon_builtins.def * config/arm/arm_neon_builtins.def (vld1_x2): Updated entries. (vld1q_x2): New entries, but comes from the old vld1_x2 * config/arm/neon.md (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from neon_vld1_x2<mode>. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vld1_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vld1_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 156 ++++++++++++++++-- gcc/config/arm/arm_neon_builtins.def | 3 +- gcc/config/arm/neon.md | 10 +- .../gcc.target/arm/simd/vld1_base_xN_1.c | 66 ++++++++ .../gcc.target/arm/simd/vld1_bf16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vld1_fp16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vld1_p64_xN_1.c | 13 ++ 7 files changed, 254 insertions(+), 20 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index df3e23b6e95..7650c066e20 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -10307,6 +10307,15 @@ vld1_p64 (const poly64_t * __a) return (poly64x1_t) { *__a }; } +__extension__ extern __inline poly64x1x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p64_x2 (const poly64_t * __a) +{ + union { poly64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #pragma GCC pop_options __extension__ extern __inline int8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10336,6 +10345,42 @@ vld1_s64 (const int64_t * __a) return (int64x1_t) { *__a }; } +__extension__ extern __inline int8x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s8_x2 (const int8_t * __a) +{ + union { int8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s16_x2 (const int16_t * __a) +{ + union { int16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline int32x2x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s32_x2 (const int32_t * __a) +{ + union { int32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline int64x1x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_s64_x2 (const int64_t * __a) +{ + union { int64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + #if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) __extension__ extern __inline float16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -10352,6 +10397,26 @@ vld1_f32 (const float32_t * __a) return (float32x2_t)__builtin_neon_vld1v2sf ((const __builtin_neon_sf *) __a); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline float16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f16_x2 (const float16_t * __a) +{ + union { float16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4hf (__a); + return __rv.__i; +} +#endif + +__extension__ extern __inline float32x2x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_f32_x2 (const float32_t * __a) +{ + union { float32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v2sf ((const __builtin_neon_sf *) __a); + return __rv.__i; +} + __extension__ extern __inline uint8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_u8 (const uint8_t * __a) @@ -10380,6 +10445,42 @@ vld1_u64 (const uint64_t * __a) return (uint64x1_t) { *__a }; } +__extension__ extern __inline uint8x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u8_x2 (const uint8_t * __a) +{ + union { uint8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u16_x2 (const uint16_t * __a) +{ + union { uint16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint32x2x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u32_x2 (const uint32_t * __a) +{ + union { uint32x2x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v2si ((const __builtin_neon_si *) __a); + return __rv.__i; +} + +__extension__ extern __inline uint64x1x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_u64_x2 (const uint64_t * __a) +{ + union { uint64x1x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2di ((const __builtin_neon_di *) __a); + return __rv.__i; +} + __extension__ extern __inline poly8x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1_p8 (const poly8_t * __a) @@ -10394,6 +10495,24 @@ vld1_p16 (const poly16_t * __a) return (poly16x4_t)__builtin_neon_vld1v4hi ((const __builtin_neon_hi *) __a); } +__extension__ extern __inline poly8x8x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p8_x2 (const poly8_t * __a) +{ + union { poly8x8x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v8qi ((const __builtin_neon_qi *) __a); + return __rv.__i; +} + +__extension__ extern __inline poly16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_p16_x2 (const poly16_t * __a) +{ + union { poly16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4hi ((const __builtin_neon_hi *) __a); + return __rv.__i; +} + #pragma GCC push_options #pragma GCC target ("fpu=crypto-neon-fp-armv8") __extension__ extern __inline poly64x2_t @@ -10408,7 +10527,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p64_x2 (const poly64_t * __a) { union { poly64x2x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x2v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10464,7 +10583,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s8_x2 (const int8_t * __a) { union { int8x16x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10473,7 +10592,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s16_x2 (const int16_t * __a) { union { int16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -10482,7 +10601,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s32_x2 (const int32_t * __a) { union { int32x4x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x2v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -10491,7 +10610,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_s64_x2 (const int64_t * __a) { union { int64x2x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x2v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10589,7 +10708,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f16_x2 (const float16_t * __a) { union { float16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8hf (__a); + __rv.__o = __builtin_neon_vld1q_x2v8hf (__a); return __rv.__i; } #endif @@ -10599,7 +10718,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_f32_x2 (const float32_t * __a) { union { float32x4x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v4sf ((const __builtin_neon_sf *) __a); + __rv.__o = __builtin_neon_vld1q_x2v4sf ((const __builtin_neon_sf *) __a); return __rv.__i; } @@ -10676,7 +10795,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u8_x2 (const uint8_t * __a) { union { uint8x16x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10685,7 +10804,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u16_x2 (const uint16_t * __a) { union { uint16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -10694,7 +10813,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u32_x2 (const uint32_t * __a) { union { uint32x4x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v4si ((const __builtin_neon_si *) __a); + __rv.__o = __builtin_neon_vld1q_x2v4si ((const __builtin_neon_si *) __a); return __rv.__i; } @@ -10703,7 +10822,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_u64_x2 (const uint64_t * __a) { union { uint64x2x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v2di ((const __builtin_neon_di *) __a); + __rv.__o = __builtin_neon_vld1q_x2v2di ((const __builtin_neon_di *) __a); return __rv.__i; } @@ -10798,7 +10917,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p8_x2 (const poly8_t * __a) { union { poly8x16x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v16qi ((const __builtin_neon_qi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v16qi ((const __builtin_neon_qi *) __a); return __rv.__i; } @@ -10807,7 +10926,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_p16_x2 (const poly16_t * __a) { union { poly16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8hi ((const __builtin_neon_hi *) __a); + __rv.__o = __builtin_neon_vld1q_x2v8hi ((const __builtin_neon_hi *) __a); return __rv.__i; } @@ -20816,6 +20935,15 @@ vld1_bf16 (bfloat16_t const * __ptr) return __builtin_neon_vld1v4bf (__ptr); } +__extension__ extern __inline bfloat16x4x2_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vld1_bf16_x2 (const bfloat16_t * __ptr) +{ + union { bfloat16x4x2_t __i; __builtin_neon_ti __o; } __rv; + __rv.__o = __builtin_neon_vld1_x2v4bf ((const __builtin_neon_bf *) __ptr); + return __rv.__i; +} + __extension__ extern __inline bfloat16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16 (const bfloat16_t * __ptr) @@ -20828,7 +20956,7 @@ __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vld1q_bf16_x2 (const bfloat16_t * __ptr) { union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __rv; - __rv.__o = __builtin_neon_vld1_x2v8bf ((const __builtin_neon_bf *) __ptr); + __rv.__o = __builtin_neon_vld1q_x2v8bf ((const __builtin_neon_bf *) __ptr); return __rv.__i; } diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 12f78800588..f988a63caea 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -298,7 +298,8 @@ VAR1 (TERNOP, vtbx1, v8qi) VAR1 (TERNOP, vtbx2, v8qi) VAR1 (TERNOP, vtbx3, v8qi) VAR1 (TERNOP, vtbx4, v8qi) -VAR7 (LOAD1, vld1_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) +VAR7 (LOAD1, vld1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (LOAD1, vld1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (LOAD1, vld1_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (LOAD1, vld1_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR13 (LOAD1, vld1, diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 2fa4f85b820..0a281c87ee5 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -4957,11 +4957,11 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_load1_1reg<q>")] ) -(define_insn "neon_vld1_x2<mode>" - [(set (match_operand:OI 0 "s_register_operand" "=w") - (unspec:OI [(match_operand:OI 1 "neon_struct_operand" "Um") - (unspec:VQXBF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] - UNSPEC_VLD1))] +(define_insn "neon_vld1<VMEMX2_q>_x2<VDQX:mode>" + [(set (match_operand:VMEMX2 0 "s_register_operand" "=w") + (unspec:VMEMX2 [(match_operand:VMEMX2 1 "neon_struct_operand" "Um") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VLD1))] "TARGET_NEON" "vld1.<V_sz_elem>\t%h0, %A1" [(set_attr "type" "neon_load1_2reg<q>")] diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c new file mode 100644 index 00000000000..6b0e78d94d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_base_xN_1.c @@ -0,0 +1,66 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + +uint8x8x2_t test_vld1_u8_x2 (uint8_t * a) +{ + return vld1_u8_x2 (a); +} + +uint16x4x2_t test_vld1_u16_x2 (uint16_t * a) +{ + return vld1_u16_x2 (a); +} + +uint32x2x2_t test_vld1_u32_x2 (uint32_t * a) +{ + return vld1_u32_x2 (a); +} + +uint64x1x2_t test_vld1_u64_x2 (uint64_t * a) +{ + return vld1_u64_x2 (a); +} + +int8x8x2_t test_vld1_s8_x2 (int8_t * a) +{ + return vld1_s8_x2 (a); +} + +int16x4x2_t test_vld1_s16_x2 (int16_t * a) +{ + return vld1_s16_x2 (a); +} + +int32x2x2_t test_vld1_s32_x2 (int32_t * a) +{ + return vld1_s32_x2 (a); +} + +int64x1x2_t test_vld1_s64_x2 (int64_t * a) +{ + return vld1_s64_x2 (a); +} + +float32x2x2_t test_vld1_f32_x2 (float32_t * a) +{ + return vld1_f32_x2 (a); +} + +poly8x8x2_t test_vld1_p8_x2 (poly8_t * a) +{ + return vld1_p8_x2 (a); +} + +poly16x4x2_t test_vld1_p16_x2 (poly16_t * a) +{ + return vld1_p16_x2 (a); +} + +/* { dg-final { scan-assembler-times {vld1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vld1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c new file mode 100644 index 00000000000..3ec7a5e1986 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_bf16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ + +#include "arm_neon.h" + +bfloat16x4x2_t test_vld1_bf16_x2 (bfloat16_t * a) +{ + return vld1_bf16_x2 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c new file mode 100644 index 00000000000..c0e5ea49142 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_fp16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_fp16_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon_fp16 } */ + +#include "arm_neon.h" + +float16x4x2_t test_vld1_f16_x2 (float16_t * a) +{ + return vld1_f16_x2 (a); +} + +/* { dg-final { scan-assembler-times {vld1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c new file mode 100644 index 00000000000..3ccea520ddc --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vld1_p64_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +poly64x1x2_t test_vld1_p64_x2 (poly64_t * a) +{ + return vld1_p64_x2 (a); +} + +/* { dg-final { scan-assembler-times {vld1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ -- 2.25.1
