On Wed, Oct 18, 2023 at 4:10 PM Haochen Jiang <haochen.ji...@intel.com> wrote: > > Hi all, > > I just found that since ISAs enabled on Sierra Forest changed, clients since > Arrow Lake will wrongly enable ENQCMD according to the current code. > > To avoid messing up again in the future, I changed the dependency on how ISAs > are enabled currently by making clients depending on clients and Atom servers > depending on Atom servers, which makes no functionality difference on > Clearwater Forest. > > Also, revise the current out of date documentation in texi file. > > Regtested on x86_64-pc-linux-gnu. Ok for trunk? Ok. > > Thx, > Haochen > > gcc/ChangeLog: > > * config/i386/i386.h: Correct the ISA enabled for Arrow Lake. > Also make Clearwater Forest depends on Sierra Forest. > * doc/invoke.texi: Correct documentation. > --- > gcc/config/i386/i386.h | 7 ++++--- > gcc/doc/invoke.texi | 15 ++++++++------- > 2 files changed, 12 insertions(+), 10 deletions(-) > > diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h > index abfe1672c41..92a7982c87f 100644 > --- a/gcc/config/i386/i386.h > +++ b/gcc/config/i386/i386.h > @@ -2401,11 +2401,12 @@ constexpr wide_int_bitmask PTA_GRANITERAPIDS = > PTA_SAPPHIRERAPIDS | PTA_AMX_FP16 > constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS > | PTA_AMX_COMPLEX; > constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT; > -constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_SIERRAFOREST; > +constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_ALDERLAKE | PTA_AVXIFMA > + | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_UINTR; > constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16 > | PTA_SHA512 | PTA_SM3 | PTA_SM4; > -constexpr wide_int_bitmask PTA_CLEARWATERFOREST = PTA_ARROWLAKE_S | > PTA_PREFETCHI > - | PTA_USER_MSR; > +constexpr wide_int_bitmask PTA_CLEARWATERFOREST = PTA_SIERRAFOREST | > PTA_AVXVNNIINT16 > + | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_USER_MSR | PTA_PREFETCHI; > constexpr wide_int_bitmask PTA_PANTHERLAKE = PTA_ARROWLAKE_S | PTA_PREFETCHI; > constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW > | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ; > diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi > index a0da7f9d5ac..69809db9f1b 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -32845,7 +32845,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, > PCLMUL, RDRND, XSAVE, XSAVEC, > XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, > MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, > PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, > -AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support. > +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set > +support. > > @item arrowlake-s > Intel Arrow Lake S CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, > @@ -32853,8 +32854,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, > PCLMUL, RDRND, XSAVE, XSAVEC, > XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, > MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, > PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, > -AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3 > -and SM4 instruction set support. > +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, > +SM3 and SM4 instruction set support. > > @item clearwaterforest > Intel Clearwater Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, > @@ -32862,8 +32863,8 @@ SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, > PCLMUL, RDRND, XSAVE, > XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, > MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, > LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, > AVX-VNNI, > -AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, > SM4, > -USER_MSR and PREFETCHI instruction set support. > +ENQCMD, UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, > +SHA512, SM3, SM4, USER_MSR and PREFETCHI instruction set support. > > @item pantherlake > Intel Panther Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, > @@ -32871,8 +32872,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, > PCLMUL, RDRND, XSAVE, XSAVEC, > XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, > MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, > PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, > -AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 > -and PREFETCHI instruction set support. > +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, > +SM3, SM4 and PREFETCHI instruction set support. > > @item knl > Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, > SSE3, > -- > 2.31.1 >
-- BR, Hongtao
