I am thinking what we are doing is something like we are allowing scalar mode within the vector register, so...not sure should we try to implement that within the mov pattern?
I guess we need some inputs from Jeff. e.g. diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0ecda795b38..ffced41588d 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -7621,6 +7621,9 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) } else if (V_REG_P (regno)) { + if (mode is scalar) + return true; + if (!riscv_v_ext_mode_p (mode)) return false; diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6d6a2b3748c..50bac39f125 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2035,8 +2035,8 @@ (define_insn "*movdi_32bit" (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) (define_insn "*movdi_64bit" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m,r") - (match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f,vp"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m,r,*vr,*r,*vr,*vr,*m") + (match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f,vp,vr,vr,r,m,vr"))] "TARGET_64BIT && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))"