From: Kong Lingling <lingling.k...@intel.com>
The APX enabled hardware should also be AVX10 enabled, thus for map2/3 insns
with evex counterpart, we assume auto promotion to EGPR under APX_F if the
insn uses GPR32. So for below insns, we disabled EGPR usage for their sse
mnenomics, while allowing egpr generation of their v prefixed mnemonics.
insn list:
1. pabsb/pabsw/pabsd
2. pextrb/pextrw/pextrd/pextrq
3. pinsrb/pinsrd/pinsrq
4. pshufb
5. extractps/insertps
6. pmaddubsw
7. pmulhrsw
8. packusdw
9. palignr
10. movntdqa
11. mpsadbw
12. pmuldq/pmulld
13. pmaxsb/pmaxsd, pminsb/pminsd
pmaxud/pmaxuw, pminud/pminuw
14. (pmovsxbw/pmovsxbd/pmovsxbq,
pmovsxwd/pmovsxwq, pmovsxdq
pmovzxbw/pmovzxbd/pmovzxbq,
pmovzxwd/pmovzxwq, pmovzxdq)
15. aesdec/aesdeclast, aesenc/aesenclast
16. pclmulqdq
17. gf2p8affineqb/gf2p8affineinvqb/gf2p8mulb
gcc/ChangeLog:
* config/i386/i386.md (*movhi_internal): Split out non-gpr
supported pextrw with mem constraint to avx/noavx alternatives,
set Bt and attr gpr32 0 to the noavx alternative.
(*mov<mode>_internal): Likewise.
* config/i386/mmx.md (mmx_pshufbv8qi3): Change "r/m/Bm" to
"h/Bt/BT" and set_attr gpr32 0 for noavx alternative.
(mmx_pshufbv4qi3): Likewise.
(*mmx_pinsrd): Likewise.
(*mmx_pinsrb): Likewise.
(*pinsrb): Likewise.
(mmx_pshufbv8qi3): Likewise.
(mmx_pshufbv4qi3): Likewise.
(@sse4_1_insertps_<mode>): Likewise.
(*mmx_pextrw): Split altrenatives and map non-EGPR
constraints, attr_gpr32 and attr_isa to noavx mnemonics.
(*movv2qi_internal): Likewise.
(*pextrw): Likewise.
(*mmx_pextrb): Likewise.
(*mmx_pextrb_zext): Likewise.
(*pextrb): Likewise.
(*pextrb_zext): Likewise.
(vec_extractv2si_1): Likewise.
(vec_extractv2si_1_zext): Likewise.
* config/i386/sse.md: (vi128_h_r): New mode attr for
pinsr{bw}/pextr{bw} with reg operand.
(*abs<mode>2): Split altrenatives and %v in mnemonics, map
non-EGPR constraints, gpr32 and isa attrs to noavx mnemonics.
(*vec_extract<mode>): Likewise.
(*vec_extract<mode>): Likewise for HFBF pattern.
(*vec_extract<PEXTR_MODE12:mode>_zext): Likewise.
(*vec_extractv4si_1): Likewise.
(*vec_extractv4si_zext): Likewise.
(*vec_extractv2di_1): Likewise.
(*vec_concatv2si_sse4_1): Likewise.
(<sse2p4_1>_pinsr<ssemodesuffix>): Likewise.
(vec_concatv2di): Likewise.
(*sse4_1_<code>v2qiv2di2<mask_name>_1): Likewise.
(ssse3_avx2>_pshufb<mode>3<mask_name>): Change "r/m/Bm" to
"h/Bt/BT" and set_attr gpr32 0 for noavx alternative, split
%v for avx/noavx alternatives if necessary.
(*vec_concatv2sf_sse4_1): Likewise.
(*sse4_1_extractps): Likewise.
(vec_set<mode>_0): Likewise for VI4F_128.
(*vec_setv4sf_sse4_1): Likewise.
(@sse4_1_insertps<mode>): Likewise.
(ssse3_pmaddubsw128): Likewise.
(*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>): Likewise.
(<sse4_1_avx2>_packusdw<mask_name>): Likewise.
(<ssse3_avx2>_palignr<mode>): Likewise.
(<vi8_sse4_1_avx2_avx512>_movntdqa): Likewise.
(<sse4_1_avx2>_mpsadbw): Likewise.
(*sse4_1_mulv2siv2di3<mask_name>): Likewise.
(*<sse4_1_avx2>_mul<mode>3<mask_name>): Likewise.
(*sse4_1_<code><mode>3<mask_name>): Likewise.
(*<code>v8hi3): Likewise.
(*<code>v16qi3): Likewise.
(*sse4_1_<code>v8qiv8hi2<mask_name>_1): Likewise.
(*sse4_1_zero_extendv8qiv8hi2_3): Likewise.
(*sse4_1_zero_extendv8qiv8hi2_4): Likewise.
(*sse4_1_<code>v4qiv4si2<mask_name>_1): Likewise.
(*sse4_1_<code>v4hiv4si2<mask_name>_1): Likewise.
(*sse4_1_zero_extendv4hiv4si2_3): Likewise.
(*sse4_1_zero_extendv4hiv4si2_4): Likewise.
(*sse4_1_<code>v2hiv2di2<mask_name>_1): Likewise.
(*sse4_1_<code>v2siv2di2<mask_name>_1): Likewise.
(*sse4_1_zero_extendv2siv2di2_3): Likewise.
(*sse4_1_zero_extendv2siv2di2_4): Likewise.
(aesdec): Likewise.
(aesdeclast): Likewise.
(aesenc): Likewise.
(aesenclast): Likewise.
(pclmulqdq): Likewise.
(vgf2p8affineinvqb_<mode><mask_name>): Likewise.
(vgf2p8affineqb_<mode><mask_name>): Likewise.
(vgf2p8mulb_<mode><mask_name>): Likewise.
---
gcc/config/i386/i386.md | 50 ++++---
gcc/config/i386/mmx.md | 159 ++++++++++++--------
gcc/config/i386/sse.md | 315 ++++++++++++++++++++++++++--------------
3 files changed, 339 insertions(+), 185 deletions(-)
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 4c305e72389..8ec249b268d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2868,9 +2868,9 @@ (define_peephole2
(define_insn "*movhi_internal"
[(set (match_operand:HI 0 "nonimmediate_operand"
- "=r,r,r,m ,*k,*k ,r ,m ,*k ,?r,?*v,*v,*v,*v,m")
+ "=r,r,r,m ,*k,*k ,r ,m ,*k ,?r,?*v,*v,*v,*v,Bt,m")
(match_operand:HI 1 "general_operand"
- "r ,n,m,rn,r ,*km,*k,*k,CBC,*v,r ,C ,*v,m ,*v"))]
+ "r ,n,m,rn,r ,*km,*k,*k,CBC,*v,r ,C ,*v,m ,*x,*v"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& ix86_hardreg_mov_ok (operands[0], operands[1])"
{
@@ -2904,8 +2904,10 @@ (define_insn "*movhi_internal"
if (SSE_REG_P (operands[0]))
return "%vpinsrw\t{$0, %1, %d0|%d0, %1, 0}";
+ else if (!TARGET_AVX)
+ return "pextrw\t{$0, %1, %0|%0, %1, 0}";
else
- return "%vpextrw\t{$0, %1, %0|%0, %1, 0}";
+ return "vpextrw\t{$0, %1, %0|%0, %1, 0}";
case TYPE_MSKLOG:
if (operands[1] == const0_rtx)
@@ -2925,15 +2927,21 @@ (define_insn "*movhi_internal"
(cond [(eq_attr "alternative" "9,10,11,12,13")
(const_string "sse2")
(eq_attr "alternative" "14")
- (const_string "sse4")
+ (const_string "sse4_noavx")
+ (eq_attr "alternative" "15")
+ (const_string "avx")
]
(const_string "*")))
+ (set (attr "gpr32")
+ (if_then_else (eq_attr "alternative" "14")
+ (const_string "0")
+ (const_string "1")))
(set (attr "type")
(cond [(eq_attr "alternative" "4,5,6,7")
(const_string "mskmov")
(eq_attr "alternative" "8")
(const_string "msklog")
- (eq_attr "alternative" "13,14")
+ (eq_attr "alternative" "13,14,15")
(if_then_else (match_test "TARGET_AVX512FP16")
(const_string "ssemov")
(const_string "sselog1"))
@@ -2958,7 +2966,7 @@ (define_insn "*movhi_internal"
(set (attr "prefix")
(cond [(eq_attr "alternative" "4,5,6,7,8")
(const_string "vex")
- (eq_attr "alternative" "9,10,11,12,13,14")
+ (eq_attr "alternative" "9,10,11,12,13,14,15")
(const_string "maybe_evex")
]
(const_string "orig")))
@@ -2967,7 +2975,7 @@ (define_insn "*movhi_internal"
(if_then_else (match_test "TARGET_AVX512FP16")
(const_string "HI")
(const_string "SI"))
- (eq_attr "alternative" "13,14")
+ (eq_attr "alternative" "13,14,15")
(if_then_else (match_test "TARGET_AVX512FP16")
(const_string "HI")
(const_string "TI"))
@@ -4320,9 +4328,9 @@ (define_mode_attr hfbfconstf
(define_insn "*mov<mode>_internal"
[(set (match_operand:HFBF 0 "nonimmediate_operand"
- "=?r,?r,?r,?m,v,v,?r,m,?v,v")
+ "=?r,?r,?r,?m,v,v,?r,Bt,m,?v,v")
(match_operand:HFBF 1 "general_operand"
- "r ,F ,m ,r<hfbfconstf>,C,v, v,v,r ,m"))]
+ "r ,F ,m ,r<hfbfconstf>,C,v, v,v,v,r ,m"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))
&& (lra_in_progress
|| reload_completed
@@ -4347,8 +4355,10 @@ (define_insn "*mov<mode>_internal"
if (SSE_REG_P (operands[0]))
return "%vpinsrw\t{$0, %1, %d0|%d0, %1, 0}";
+ else if (!TARGET_AVX)
+ return "pextrw\t{$0, %1, %0|%0, %1, 0}";
else
- return "%vpextrw\t{$0, %1, %0|%0, %1, 0}";
+ return "vpextrw\t{$0, %1, %0|%0, %1, 0}";
default:
if (get_attr_mode (insn) == MODE_SI)
@@ -4358,18 +4368,24 @@ (define_insn "*mov<mode>_internal"
}
}
[(set (attr "isa")
- (cond [(eq_attr "alternative" "4,5,6,8,9")
+ (cond [(eq_attr "alternative" "4,5,6,9,10")
(const_string "sse2")
(eq_attr "alternative" "7")
- (const_string "sse4")
+ (const_string "sse4_noavx")
+ (eq_attr "alternative" "8")
+ (const_string "avx")
]
(const_string "*")))
+ (set (attr "gpr32")
+ (if_then_else (eq_attr "alternative" "8")
+ (const_string "0")
+ (const_string "1")))
(set (attr "type")
(cond [(eq_attr "alternative" "4")
(const_string "sselog1")
- (eq_attr "alternative" "5,6,8")
+ (eq_attr "alternative" "5,6,9")
(const_string "ssemov")
- (eq_attr "alternative" "7,9")
+ (eq_attr "alternative" "7,8,10")
(if_then_else
(match_test ("TARGET_AVX512FP16"))
(const_string "ssemov")
@@ -4389,19 +4405,19 @@ (define_insn "*mov<mode>_internal"
]
(const_string "imov")))
(set (attr "prefix")
- (cond [(eq_attr "alternative" "4,5,6,7,8,9")
+ (cond [(eq_attr "alternative" "4,5,6,7,8,9,10")
(const_string "maybe_vex")
]
(const_string "orig")))
(set (attr "mode")
(cond [(eq_attr "alternative" "4")
(const_string "V4SF")
- (eq_attr "alternative" "6,8")
+ (eq_attr "alternative" "6,9")
(if_then_else
(match_test "TARGET_AVX512FP16")
(const_string "HI")
(const_string "SI"))
- (eq_attr "alternative" "7,9")
+ (eq_attr "alternative" "7,8,10")
(if_then_else
(match_test "TARGET_AVX512FP16")
(const_string "HI")
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index ef578222945..63803c89f2b 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -418,9 +418,9 @@ (define_expand "movv2qi"
(define_insn "*movv2qi_internal"
[(set (match_operand:V2QI 0 "nonimmediate_operand"
- "=r,r,r,m ,v,v,v,m,r,v")
+ "=r,r,r,m ,v,v,v,Bt,m,r,v")
(match_operand:V2QI 1 "general_operand"
- "r ,C,m,rC,C,v,m,v,v,r"))]
+ "r ,C,m,rC,C,v,m,x,v,v,r"))]
"!(MEM_P (operands[0]) && MEM_P (operands[1]))"
{
switch (get_attr_type (insn))
@@ -442,8 +442,10 @@ (define_insn "*movv2qi_internal"
if (SSE_REG_P (operands[0]))
return "%vpinsrw\t{$0, %1, %d0|%d0, %1, 0}";
+ else if (!TARGET_AVX)
+ return "pextrw\t{$0, %1, %0|%0, %1, 0}";
else
- return "%vpextrw\t{$0, %1, %0|%0, %1, 0}";
+ return "vpextrw\t{$0, %1, %0|%0, %1, 0}";
case TYPE_SSEMOV:
return ix86_output_ssemov (insn, operands);
@@ -453,20 +455,26 @@ (define_insn "*movv2qi_internal"
}
}
[(set (attr "isa")
- (cond [(eq_attr "alternative" "6,8,9")
+ (cond [(eq_attr "alternative" "6,9,10")
(const_string "sse2")
(eq_attr "alternative" "7")
- (const_string "sse4")
+ (const_string "sse4_noavx")
+ (eq_attr "alternative" "8")
+ (const_string "avx")
]
(const_string "*")))
+ (set (attr "gpr32")
+ (if_then_else (eq_attr "alternative" "7")
+ (const_string "0")
+ (const_string "1")))
(set (attr "type")
- (cond [(eq_attr "alternative" "6,7")
+ (cond [(eq_attr "alternative" "6,7,8")
(if_then_else (match_test "TARGET_AVX512FP16")
(const_string "ssemov")
(const_string "sselog1"))
(eq_attr "alternative" "4")
(const_string "sselog1")
- (eq_attr "alternative" "5,8,9")
+ (eq_attr "alternative" "5,9,10")
(const_string "ssemov")
(match_test "optimize_function_for_size_p (cfun)")
(const_string "imov")
@@ -483,16 +491,16 @@ (define_insn "*movv2qi_internal"
]
(const_string "imov")))
(set (attr "prefix")
- (cond [(eq_attr "alternative" "4,5,6,7,8,9")
+ (cond [(eq_attr "alternative" "4,5,6,7,8,9,10")
(const_string "maybe_evex")
]
(const_string "orig")))
(set (attr "mode")
- (cond [(eq_attr "alternative" "6,7")
+ (cond [(eq_attr "alternative" "6,7,8")
(if_then_else (match_test "TARGET_AVX512FP16")
(const_string "HI")
(const_string "TI"))
- (eq_attr "alternative" "8,9")
+ (eq_attr "alternative" "9,10")
(if_then_else (match_test "TARGET_AVX512FP16")
(const_string "HI")
(const_string "SI"))
@@ -526,9 +534,9 @@ (define_insn "*movv2qi_internal"
]
(const_string "HI")))
(set (attr "preferred_for_speed")
- (cond [(eq_attr "alternative" "8")
+ (cond [(eq_attr "alternative" "9")
(symbol_ref "TARGET_INTER_UNIT_MOVES_FROM_VEC")
- (eq_attr "alternative" "9")
+ (eq_attr "alternative" "10")
(symbol_ref "TARGET_INTER_UNIT_MOVES_TO_VEC")
]
(symbol_ref "true")))])
@@ -1167,7 +1175,7 @@ (define_expand "vcond<mode>v2sf"
(define_insn "@sse4_1_insertps_<mode>"
[(set (match_operand:V2FI 0 "register_operand" "=Yr,*x,v")
(unspec:V2FI
- [(match_operand:V2FI 2 "nonimmediate_operand" "Yrm,*xm,vm")
+ [(match_operand:V2FI 2 "nonimmediate_operand" "YrBt,*xBt,vm")
(match_operand:V2FI 1 "register_operand" "0,0,v")
(match_operand:SI 3 "const_0_to_255_operand")]
UNSPEC_INSERTPS))]
@@ -1193,6 +1201,7 @@ (define_insn "@sse4_1_insertps_<mode>"
}
}
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "sselog")
(set_attr "prefix_data16" "1,1,*")
(set_attr "prefix_extra" "1")
@@ -3952,7 +3961,7 @@ (define_insn "*mmx_pinsrd"
[(set (match_operand:V2SI 0 "register_operand" "=x,Yv")
(vec_merge:V2SI
(vec_duplicate:V2SI
- (match_operand:SI 2 "nonimmediate_operand" "rm,rm"))
+ (match_operand:SI 2 "nonimmediate_operand" "hBt,rm"))
(match_operand:V2SI 1 "register_operand" "0,Yv")
(match_operand:SI 3 "const_int_operand")))]
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
@@ -3971,6 +3980,7 @@ (define_insn "*mmx_pinsrd"
}
}
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "prefix_extra" "1")
(set_attr "type" "sselog")
(set_attr "length_immediate" "1")
@@ -4031,7 +4041,7 @@ (define_insn "*mmx_pinsrb"
[(set (match_operand:V8QI 0 "register_operand" "=x,YW")
(vec_merge:V8QI
(vec_duplicate:V8QI
- (match_operand:QI 2 "nonimmediate_operand" "rm,rm"))
+ (match_operand:QI 2 "nonimmediate_operand" "hBt,rm"))
(match_operand:V8QI 1 "register_operand" "0,YW")
(match_operand:SI 3 "const_int_operand")))]
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE
@@ -4057,28 +4067,31 @@ (define_insn "*mmx_pinsrb"
}
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sselog")
+ (set_attr "gpr32" "0,1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
(define_insn "*mmx_pextrw"
- [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,m")
+ [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,Bt,m")
(vec_select:HI
- (match_operand:V4HI 1 "register_operand" "y,YW,YW")
+ (match_operand:V4HI 1 "register_operand" "y,YW,YW,YW")
(parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
"(TARGET_MMX || TARGET_MMX_WITH_SSE)
&& (TARGET_SSE || TARGET_3DNOW_A)"
"@
pextrw\t{%2, %1, %k0|%k0, %1, %2}
%vpextrw\t{%2, %1, %k0|%k0, %1, %2}
- %vpextrw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "*,sse2,sse4")
- (set_attr "mmx_isa" "native,*,*")
- (set_attr "type" "mmxcvt,sselog1,sselog1")
+ pextrw\t{%2, %1, %0|%0, %1, %2}
+ vpextrw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,sse2,sse4_noavx,avx")
+ (set_attr "gpr32" "1,1,0,1")
+ (set_attr "mmx_isa" "native,*,*,*")
+ (set_attr "type" "mmxcvt,sselog1,sselog1,sselog1")
(set_attr "length_immediate" "1")
- (set_attr "prefix" "orig,maybe_vex,maybe_vex")
- (set_attr "mode" "DI,TI,TI")])
+ (set_attr "prefix" "orig,maybe_vex,maybe_vex,maybe_evex")
+ (set_attr "mode" "DI,TI,TI,TI")])
(define_insn "*mmx_pextrw_zext"
[(set (match_operand:SWI48 0 "register_operand" "=r,r")
@@ -4099,29 +4112,36 @@ (define_insn "*mmx_pextrw_zext"
(set_attr "mode" "DI,TI")])
(define_insn "*mmx_pextrb"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=h,Bt,r,m")
(vec_select:QI
- (match_operand:V8QI 1 "register_operand" "YW,YW")
+ (match_operand:V8QI 1 "register_operand" "YW,YW,YW,YW")
(parallel [(match_operand:SI 2 "const_0_to_7_operand")])))]
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
"@
- %vpextrb\t{%2, %1, %k0|%k0, %1, %2}
- %vpextrb\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog1")
+ pextrb\t{%2, %1, %k0|%k0, %1, %2}
+ pextrb\t{%2, %1, %0|%0, %1, %2}
+ vpextrb\t{%2, %1, %k0|%k0, %1, %2}
+ vpextrb\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,noavx,avx,avx")
+ (set_attr "gpr32" "1,0,1,1")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*mmx_pextrb_zext"
- [(set (match_operand:SWI248 0 "register_operand" "=r")
+ [(set (match_operand:SWI248 0 "register_operand" "=h,r")
(zero_extend:SWI248
(vec_select:QI
- (match_operand:V8QI 1 "register_operand" "YW")
+ (match_operand:V8QI 1 "register_operand" "YW,YW")
(parallel [(match_operand:SI 2 "const_0_to_7_operand")]))))]
"TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
- "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
- [(set_attr "type" "sselog1")
+ "@
+ pextrb\t{%2, %1, %k0|%k0, %1, %2}
+ vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -4131,13 +4151,14 @@ (define_insn "mmx_pshufbv8qi3"
[(set (match_operand:V8QI 0 "register_operand" "=x,Yw")
(unspec:V8QI
[(match_operand:V8QI 1 "register_operand" "0,Yw")
- (match_operand:V16QI 2 "vector_operand" "xBm,Ywm")]
+ (match_operand:V16QI 2 "vector_operand" "xBT,Ywm")]
UNSPEC_PSHUFB))]
"TARGET_SSSE3 && TARGET_MMX_WITH_SSE"
"@
pshufb\t{%2, %0|%0, %2}
vpshufb\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
@@ -4148,13 +4169,14 @@ (define_insn "mmx_pshufbv4qi3"
[(set (match_operand:V4QI 0 "register_operand" "=x,Yw")
(unspec:V4QI
[(match_operand:V4QI 1 "register_operand" "0,Yw")
- (match_operand:V16QI 2 "vector_operand" "xBm,Ywm")]
+ (match_operand:V16QI 2 "vector_operand" "xBT,Ywm")]
UNSPEC_PSHUFB))]
"TARGET_SSSE3"
"@
pshufb\t{%2, %0|%0, %2}
vpshufb\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
@@ -4414,29 +4436,31 @@ (define_split
;; Avoid combining registers from different units in a single alternative,
;; see comment above inline_secondary_memory_needed function in i386.cc
(define_insn "*vec_extractv2si_1"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=y,rm,x,x,y,x,r")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=y,hBt,rm,x,x,y,x,r")
(vec_select:SI
- (match_operand:V2SI 1 "nonimmediate_operand" " 0,x ,x,0,o,o,o")
+ (match_operand:V2SI 1 "nonimmediate_operand" " 0,x, x ,x,0,o,o,o")
(parallel [(const_int 1)])))]
"(TARGET_MMX || TARGET_MMX_WITH_SSE)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
punpckhdq\t%0, %0
- %vpextrd\t{$1, %1, %0|%0, %1, 1}
+ pextrd\t{$1, %1, %0|%0, %1, 1}
+ vpextrd\t{$1, %1, %0|%0, %1, 1}
%vpshufd\t{$0xe5, %1, %0|%0, %1, 0xe5}
shufps\t{$0xe5, %0, %0|%0, %0, 0xe5}
#
#
#"
- [(set_attr "isa" "*,sse4,sse2,noavx,*,*,*")
- (set_attr "mmx_isa" "native,*,*,*,native,*,*")
- (set_attr "type" "mmxcvt,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
+ [(set_attr "isa" "*,sse4_noavx,avx,sse2,noavx,*,*,*")
+ (set_attr "gpr32" "1,0,1,1,1,1,1,1")
+ (set_attr "mmx_isa" "native,*,*,*,*,native,*,*")
+ (set_attr "type"
"mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov")
(set (attr "length_immediate")
- (if_then_else (eq_attr "alternative" "1,2,3")
+ (if_then_else (eq_attr "alternative" "1,2,3,4")
(const_string "1")
(const_string "*")))
- (set_attr "prefix" "orig,maybe_vex,maybe_vex,orig,orig,orig,orig")
- (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
+ (set_attr "prefix" "orig,orig,maybe_evex,maybe_vex,orig,orig,orig,orig")
+ (set_attr "mode" "DI,TI,TI,TI,V4SF,SI,SI,SI")])
(define_split
[(set (match_operand:SI 0 "register_operand")
@@ -4448,15 +4472,18 @@ (define_split
"operands[1] = adjust_address (operands[1], SImode, 4);")
(define_insn "*vec_extractv2si_1_zext"
- [(set (match_operand:DI 0 "register_operand" "=r")
+ [(set (match_operand:DI 0 "register_operand" "=h,r")
(zero_extend:DI
(vec_select:SI
- (match_operand:V2SI 1 "register_operand" "x")
+ (match_operand:V2SI 1 "register_operand" "x,x")
(parallel [(const_int 1)]))))]
"(TARGET_MMX || TARGET_MMX_WITH_SSE)
&& TARGET_64BIT && TARGET_SSE4_1"
- "%vpextrd\t{$1, %1, %k0|%k0, %1, 1}"
- [(set_attr "type" "sselog1")
+ "@
+ pextrd\t{$1, %1, %k0|%k0, %1, 1}
+ vpextrd\t{$1, %1, %k0|%k0, %1, 1}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -4606,7 +4633,7 @@ (define_insn "*pinsrb"
[(set (match_operand:V4QI 0 "register_operand" "=x,YW")
(vec_merge:V4QI
(vec_duplicate:V4QI
- (match_operand:QI 2 "nonimmediate_operand" "rm,rm"))
+ (match_operand:QI 2 "nonimmediate_operand" "hBt,rm"))
(match_operand:V4QI 1 "register_operand" "0,YW")
(match_operand:SI 3 "const_int_operand")))]
"TARGET_SSE4_1
@@ -4631,6 +4658,7 @@ (define_insn "*pinsrb"
}
}
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
@@ -4638,15 +4666,17 @@ (define_insn "*pinsrb"
(set_attr "mode" "TI")])
(define_insn "*pextrw"
- [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,m")
+ [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,Bt,m")
(vec_select:HI
- (match_operand:V2HI 1 "register_operand" "YW,YW")
+ (match_operand:V2HI 1 "register_operand" "YW,YW,YW")
(parallel [(match_operand:SI 2 "const_0_to_1_operand")])))]
"TARGET_SSE2"
"@
%vpextrw\t{%2, %1, %k0|%k0, %1, %2}
- %vpextrw\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "*,sse4")
+ pextrw\t{%2, %1, %0|%0, %1, %2}
+ vpextrw\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "*,sse4_noavx,avx")
+ (set_attr "gpr32" "1,0,1")
(set_attr "type" "sselog1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -4666,29 +4696,36 @@ (define_insn "*pextrw_zext"
(set_attr "mode" "TI")])
(define_insn "*pextrb"
- [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m")
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=h,Bt,r,m")
(vec_select:QI
- (match_operand:V4QI 1 "register_operand" "YW,YW")
+ (match_operand:V4QI 1 "register_operand" "YW,YW,YW,YW")
(parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
"TARGET_SSE4_1"
"@
- %vpextrb\t{%2, %1, %k0|%k0, %1, %2}
- %vpextrb\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sselog1")
+ pextrb\t{%2, %1, %k0|%k0, %1, %2}
+ pextrb\t{%2, %1, %0|%0, %1, %2}
+ vpextrb\t{%2, %1, %k0|%k0, %1, %2}
+ vpextrb\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,noavx,avx,avx")
+ (set_attr "gpr32" "1,0,1,1")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*pextrb_zext"
- [(set (match_operand:SWI248 0 "register_operand" "=r")
+ [(set (match_operand:SWI248 0 "register_operand" "=h,r")
(zero_extend:SWI248
(vec_select:QI
- (match_operand:V4QI 1 "register_operand" "YW")
+ (match_operand:V4QI 1 "register_operand" "YW,YW")
(parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
"TARGET_SSE4_1"
- "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
- [(set_attr "type" "sselog1")
+ "@
+ pextrb\t{%2, %1, %k0|%k0, %1, %2}
+ vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 456713b991a..4913c34ed37 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -10840,7 +10840,7 @@ (define_insn "*vec_concatv2sf_sse4_1"
(match_operand:SF 1 "nonimmediate_operand"
" 0, 0,Yv, 0,0, v,m, 0 , m")
(match_operand:SF 2 "nonimm_or_0_operand"
- " Yr,*x,Yv, m,m, m,C,*ym, C")))]
+ " Yr,*x,Yv, Bt,Bt, m,C,*ym, C")))]
"TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
unpcklps\t{%2, %0|%0, %2}
@@ -10872,6 +10872,10 @@ (define_insn "*vec_concatv2sf_sse4_1"
(if_then_else (eq_attr "alternative" "7,8")
(const_string "native")
(const_string "*")))
+ (set (attr "gpr32")
+ (if_then_else (eq_attr "alternative" "3,4")
+ (const_string "0")
+ (const_string "1")))
(set (attr "prefix_data16")
(if_then_else (eq_attr "alternative" "3,4")
(const_string "1")
@@ -10963,7 +10967,7 @@ (define_insn "vec_set<mode>_0"
(vec_merge:VI4F_128
(vec_duplicate:VI4F_128
(match_operand:<ssescalarmode> 2 "general_operand"
- " Yr,*x,v,m,r ,m,x,v,?rm,?rm,?rm,!x,?re,!*fF"))
+ " Yr,*x,v,m,r ,m,x,v,?hBt,?hBt,?rm,!x,?re,!*fF"))
(match_operand:VI4F_128 1 "nonimm_or_0_operand"
" C , C,C,C,C ,C,0,v,0 ,0 ,x ,0 ,0 ,0")
(const_int 1)))]
@@ -11003,6 +11007,10 @@ (define_insn "vec_set<mode>_0"
(const_string "fmov")
]
(const_string "ssemov")))
+ (set (attr "gpr32")
+ (if_then_else (eq_attr "alternative" "8,9")
+ (const_string "0")
+ (const_string "1")))
(set (attr "prefix_extra")
(if_then_else (eq_attr "alternative" "8,9,10")
(const_string "1")
@@ -11175,7 +11183,7 @@ (define_insn "*vec_setv4sf_sse4_1"
[(set (match_operand:V4SF 0 "register_operand" "=Yr,*x,v")
(vec_merge:V4SF
(vec_duplicate:V4SF
- (match_operand:SF 2 "nonimmediate_operand" "Yrm,*xm,vm"))
+ (match_operand:SF 2 "nonimmediate_operand" "YrBt,*xBt,vm"))
(match_operand:V4SF 1 "register_operand" "0,0,v")
(match_operand:SI 3 "const_int_operand")))]
"TARGET_SSE4_1
@@ -11196,6 +11204,7 @@ (define_insn "*vec_setv4sf_sse4_1"
}
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sselog")
+ (set_attr "gpr32" "0,0,1")
(set_attr "prefix_data16" "1,1,*")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
@@ -11270,7 +11279,7 @@ (define_insn_and_split "*vec_setv2di_0_zero_extendsi_1"
(define_insn "@sse4_1_insertps_<mode>"
[(set (match_operand:VI4F_128 0 "register_operand" "=Yr,*x,v")
(unspec:VI4F_128
- [(match_operand:VI4F_128 2 "nonimmediate_operand" "Yrm,*xm,vm")
+ [(match_operand:VI4F_128 2 "nonimmediate_operand" "YrBt,*xBt,vm")
(match_operand:VI4F_128 1 "register_operand" "0,0,v")
(match_operand:SI 3 "const_0_to_255_operand")]
UNSPEC_INSERTPS))]
@@ -11296,6 +11305,7 @@ (define_insn "@sse4_1_insertps_<mode>"
}
}
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "sselog")
(set_attr "prefix_data16" "1,1,*")
(set_attr "prefix_extra" "1")
@@ -11373,7 +11383,7 @@ (define_insn_and_split "*vec_extractv4sf_0"
"operands[1] = gen_lowpart (SFmode, operands[1]);")
(define_insn_and_split "*sse4_1_extractps"
- [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,Yv,Yv")
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=hBt,hBt,rm,Yv,Yv")
(vec_select:SF
(match_operand:V4SF 1 "register_operand" "Yr,*x,v,0,v")
(parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
@@ -11407,6 +11417,7 @@ (define_insn_and_split "*sse4_1_extractps"
DONE;
}
[(set_attr "isa" "noavx,noavx,avx,noavx,avx")
+ (set_attr "gpr32" "0,0,1,1,1")
(set_attr "type" "sselog,sselog,sselog,*,*")
(set_attr "prefix_data16" "1,1,1,*,*")
(set_attr "prefix_extra" "1,1,1,*,*")
@@ -12271,9 +12282,9 @@ (define_insn_and_split "*vec_extract<mode>_0"
"operands[1] = gen_lowpart (<ssescalarmode>mode, operands[1]);")
(define_insn "*vec_extract<mode>"
- [(set (match_operand:HFBF 0 "register_sse4nonimm_operand" "=?r,m,x,v")
+ [(set (match_operand:HFBF 0 "register_sse4nonimm_operand" "=?r,Bt,m,x,v")
(vec_select:HFBF
- (match_operand:<ssevecmode> 1 "register_operand" "v,v,0,v")
+ (match_operand:<ssevecmode> 1 "register_operand" "v,x,v,0,v")
(parallel
[(match_operand:SI 2 "const_0_to_7_operand")])))]
"TARGET_SSE2"
@@ -12283,12 +12294,14 @@ (define_insn "*vec_extract<mode>"
case 0:
return "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}";
case 1:
- return "%vpextrw\t{%2, %1, %0|%0, %1, %2}";
-
+ return "pextrw\t{%2, %1, %0|%0, %1, %2}";
case 2:
+ return "vpextrw\t{%2, %1, %0|%0, %1, %2}";
+
+ case 3:
operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
return "psrldq\t{%2, %0|%0, %2}";
- case 3:
+ case 4:
operands[2] = GEN_INT (INTVAL (operands[2]) * 2);
return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
@@ -12296,8 +12309,9 @@ (define_insn "*vec_extract<mode>"
gcc_unreachable ();
}
}
- [(set_attr "isa" "*,sse4,noavx,avx")
- (set_attr "type" "sselog1,sselog1,sseishft1,sseishft1")
+ [(set_attr "isa" "*,sse4_noavx,avx,noavx,avx")
+ (set_attr "gpr32" "1,0,1,1,1")
+ (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "TI")])
@@ -15659,7 +15673,7 @@ (define_insn "*sse4_1_mulv2siv2di3<mask_name>"
(parallel [(const_int 0) (const_int 2)])))
(sign_extend:V2DI
(vec_select:V2SI
- (match_operand:V4SI 2 "vector_operand" "YrBm,*xBm,vm")
+ (match_operand:V4SI 2 "vector_operand" "YrBT,*xBT,vm")
(parallel [(const_int 0) (const_int 2)])))))]
"TARGET_SSE4_1 && <mask_avx512vl_condition>
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
@@ -15668,6 +15682,7 @@ (define_insn "*sse4_1_mulv2siv2di3<mask_name>"
pmuldq\t{%2, %0|%0, %2}
vpmuldq\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,vex")
@@ -15905,7 +15920,7 @@ (define_insn "*<sse4_1_avx2>_mul<mode>3<mask_name>"
[(set (match_operand:VI4_AVX512F 0 "register_operand" "=Yr,*x,v")
(mult:VI4_AVX512F
(match_operand:VI4_AVX512F 1 "bcst_vector_operand" "%0,0,v")
- (match_operand:VI4_AVX512F 2 "bcst_vector_operand"
"YrBm,*xBm,vmBr")))]
+ (match_operand:VI4_AVX512F 2 "bcst_vector_operand"
"YrBT,*xBT,vmBr")))]
"TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)
&& <mask_mode512bit_condition>"
"@
@@ -15913,6 +15928,7 @@ (define_insn "*<sse4_1_avx2>_mul<mode>3<mask_name>"
pmulld\t{%2, %0|%0, %2}
vpmulld\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "<bcst_mask_prefix4>")
@@ -16717,7 +16733,7 @@ (define_insn "*sse4_1_<code><mode>3<mask_name>"
[(set (match_operand:VI14_128 0 "register_operand" "=Yr,*x,<v_Yw>")
(smaxmin:VI14_128
(match_operand:VI14_128 1 "vector_operand" "%0,0,<v_Yw>")
- (match_operand:VI14_128 2 "vector_operand" "YrBm,*xBm,<v_Yw>m")))]
+ (match_operand:VI14_128 2 "vector_operand" "YrBT,*xBT,<v_Yw>m")))]
"TARGET_SSE4_1
&& <mask_mode512bit_condition>
&& !(MEM_P (operands[1]) && MEM_P (operands[2]))"
@@ -16728,6 +16744,7 @@ (define_insn "*sse4_1_<code><mode>3<mask_name>"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseiadd")
(set_attr "prefix_extra" "1")
+ (set_attr "gpr32" "0,0,1")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "TI")])
@@ -16735,13 +16752,14 @@ (define_insn "*<code>v8hi3"
[(set (match_operand:V8HI 0 "register_operand" "=x,Yw")
(smaxmin:V8HI
(match_operand:V8HI 1 "vector_operand" "%0,Yw")
- (match_operand:V8HI 2 "vector_operand" "xBm,Ywm")))]
+ (match_operand:V8HI 2 "vector_operand" "xBT,Ywm")))]
"TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int>w\t{%2, %0|%0, %2}
vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "gpr32" "0,1")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
@@ -16809,6 +16827,7 @@ (define_insn "*sse4_1_<code><mode>3<mask_name>"
vp<maxmin_int><ssemodesuffix>\t{%2, %1,
%0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
(set_attr "type" "sseiadd")
+ (set_attr "gpr32" "0,0,1")
(set_attr "prefix_extra" "1,1,*")
(set_attr "prefix" "orig,orig,vex")
(set_attr "mode" "TI")])
@@ -16817,12 +16836,13 @@ (define_insn "*<code>v16qi3"
[(set (match_operand:V16QI 0 "register_operand" "=x,Yw")
(umaxmin:V16QI
(match_operand:V16QI 1 "vector_operand" "%0,Yw")
- (match_operand:V16QI 2 "vector_operand" "xBm,Ywm")))]
+ (match_operand:V16QI 2 "vector_operand" "xBT,Ywm")))]
"TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
p<maxmin_int>b\t{%2, %0|%0, %2}
vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "type" "sseiadd")
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
@@ -18813,7 +18833,7 @@ (define_insn "<sse2p4_1>_pinsr<ssemodesuffix>"
[(set (match_operand:PINSR_MODE 0 "register_operand" "=x,x,x,x,v,v,&x")
(vec_merge:PINSR_MODE
(vec_duplicate:PINSR_MODE
- (match_operand:<ssescalarmode> 2 "nonimmediate_operand"
"r,m,r,m,r,m,x"))
+ (match_operand:<ssescalarmode> 2 "nonimmediate_operand"
"h,Bt,r,m,r,m,x"))
(match_operand:PINSR_MODE 1 "register_operand" "0,0,x,x,v,v,x")
(match_operand:SI 3 "const_int_operand")))]
"TARGET_SSE2
@@ -18850,6 +18870,7 @@ (define_insn "<sse2p4_1>_pinsr<ssemodesuffix>"
}
[(set_attr "isa"
"noavx,noavx,avx,avx,<pinsr_evex_isa>,<pinsr_evex_isa>,avx2")
(set_attr "type" "sselog")
+ (set_attr "gpr32" "0,0,1,1,1,1,1")
(set (attr "prefix_rex")
(if_then_else
(and (not (match_test "TARGET_AVX"))
@@ -20010,17 +20031,23 @@ (define_insn_and_split "*vec_extract<mode>_0_mem"
operands[4] = gen_lowpart (<ssescalarmode>mode, operands[2]);
})
+(define_mode_attr vi128_h_r
+ [(V16QI "h") (V8HI "r")])
+
(define_insn "*vec_extract<mode>"
- [(set (match_operand:<ssescalarmode> 0 "register_sse4nonimm_operand" "=r,m")
+ [(set (match_operand:<ssescalarmode> 0 "register_sse4nonimm_operand"
"=<vi128_h_r>,r,Bt,m")
(vec_select:<ssescalarmode>
- (match_operand:PEXTR_MODE12 1 "register_operand" "YW,YW")
+ (match_operand:PEXTR_MODE12 1 "register_operand" "YW,YW,YW,YW")
(parallel
[(match_operand:SI 2 "const_0_to_<ssescalarnummask>_operand")])))]
"TARGET_SSE2"
"@
- %vpextr<ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}
- %vpextr<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "isa" "*,sse4")
+ pextr<ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}
+ vpextr<ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}
+ pextr<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}
+ vpextr<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "sse2_noavx,avx,sse4_noavx,avx")
+ (set_attr "gpr32" "1,1,0,1")
(set_attr "type" "sselog1")
(set (attr "prefix_extra")
(if_then_else
@@ -20028,20 +20055,23 @@ (define_insn "*vec_extract<mode>"
(const_string "*")
(const_string "1")))
(set_attr "length_immediate" "1")
- (set_attr "prefix" "maybe_vex,maybe_vex")
+ (set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*vec_extract<PEXTR_MODE12:mode>_zext"
- [(set (match_operand:SWI48 0 "register_operand" "=r")
+ [(set (match_operand:SWI48 0 "register_operand" "=<vi128_h_r>,r")
(zero_extend:SWI48
(vec_select:<PEXTR_MODE12:ssescalarmode>
- (match_operand:PEXTR_MODE12 1 "register_operand" "YW")
+ (match_operand:PEXTR_MODE12 1 "register_operand" "YW,YW")
(parallel
[(match_operand:SI 2
"const_0_to_<PEXTR_MODE12:ssescalarnummask>_operand")]))))]
"TARGET_SSE2"
- "%vpextr<PEXTR_MODE12:ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}"
- [(set_attr "type" "sselog1")
+ "@
+ pextr<PEXTR_MODE12:ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}
+ vpextr<PEXTR_MODE12:ssemodesuffix>\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set (attr "prefix_extra")
(if_then_else
(eq (const_string "<PEXTR_MODE12:MODE>mode") (const_string "V8HImode"))
@@ -20052,15 +20082,18 @@ (define_insn "*vec_extract<PEXTR_MODE12:mode>_zext"
(set_attr "mode" "TI")])
(define_insn "*vec_extractv16qi_zext"
- [(set (match_operand:HI 0 "register_operand" "=r")
+ [(set (match_operand:HI 0 "register_operand" "=h,r")
(zero_extend:HI
(vec_select:QI
- (match_operand:V16QI 1 "register_operand" "YW")
+ (match_operand:V16QI 1 "register_operand" "YW,YW")
(parallel
[(match_operand:SI 2 "const_0_to_15_operand")]))))]
"TARGET_SSE4_1"
- "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
- [(set_attr "type" "sselog1")
+ "@
+ pextrb\t{%2, %1, %k0|%k0, %1, %2}
+ vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "maybe_vex")
@@ -20166,24 +20199,26 @@ (define_split
"operands[1] = gen_lowpart (SImode, operands[1]);")
(define_insn "*vec_extractv4si"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm,rm,Yr,*x,Yw")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=hBt,rm,rm,Yr,*x,Yw")
(vec_select:SI
- (match_operand:V4SI 1 "register_operand" " x, v, 0, 0,Yw")
+ (match_operand:V4SI 1 "register_operand" "x, x, v, 0, 0, Yw")
(parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
"TARGET_SSE4_1"
{
switch (which_alternative)
{
case 0:
+ return "pextrd\t{%2, %1, %0|%0, %1, %2}";
case 1:
- return "%vpextrd\t{%2, %1, %0|%0, %1, %2}";
-
case 2:
+ return "vpextrd\t{%2, %1, %0|%0, %1, %2}";
+
case 3:
+ case 4:
operands[2] = GEN_INT (INTVAL (operands[2]) * 4);
return "psrldq\t{%2, %0|%0, %2}";
- case 4:
+ case 5:
operands[2] = GEN_INT (INTVAL (operands[2]) * 4);
return "vpsrldq\t{%2, %1, %0|%0, %1, %2}";
@@ -20191,25 +20226,29 @@ (define_insn "*vec_extractv4si"
gcc_unreachable ();
}
}
- [(set_attr "isa" "*,avx512dq,noavx,noavx,avx")
- (set_attr "type" "sselog1,sselog1,sseishft1,sseishft1,sseishft1")
+ [(set_attr "isa" "noavx,avx,avx512dq,noavx,noavx,avx")
+ (set_attr "type" "sselog1,sselog1,sselog1,sseishft1,sseishft1,sseishft1")
+ (set_attr "gpr32" "0,1,1,1,1,1")
(set (attr "prefix_extra")
(if_then_else (eq_attr "alternative" "0,1")
(const_string "1")
(const_string "*")))
(set_attr "length_immediate" "1")
- (set_attr "prefix" "maybe_vex,evex,orig,orig,maybe_vex")
+ (set_attr "prefix" "orig,vex,evex,orig,orig,maybe_vex")
(set_attr "mode" "TI")])
(define_insn "*vec_extractv4si_zext"
- [(set (match_operand:DI 0 "register_operand" "=r,r")
+ [(set (match_operand:DI 0 "register_operand" "=h,r,r")
(zero_extend:DI
(vec_select:SI
- (match_operand:V4SI 1 "register_operand" "x,v")
+ (match_operand:V4SI 1 "register_operand" "x,x,v")
(parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
"TARGET_64BIT && TARGET_SSE4_1"
- "%vpextrd\t{%2, %1, %k0|%k0, %1, %2}"
- [(set_attr "isa" "*,avx512dq")
+ "@
+ pextrd\t{%2, %1, %k0|%k0, %1, %2}
+ vpextrd\t{%2, %1, %k0|%k0, %1, %2}
+ vpextrd\t{%2, %1, %k0|%k0, %1, %2}"
+ [(set_attr "isa" "noavx,avx,avx512dq")
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
@@ -20239,13 +20278,14 @@ (define_insn_and_split "*vec_extractv4si_zext_mem"
})
(define_insn "*vec_extractv2di_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,rm,m,x,x,Yv,x,v,r")
+ [(set (match_operand:DI 0 "nonimmediate_operand"
"=hBt,rm,rm,m,x,x,Yv,x,v,r")
(vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" "x ,v ,v,0,x, v,x,o,o")
+ (match_operand:V2DI 1 "nonimmediate_operand" "x, x ,v ,v,0,x,
v,x,o,o")
(parallel [(const_int 1)])))]
"TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
- %vpextrq\t{$1, %1, %0|%0, %1, 1}
+ pextrq\t{$1, %1, %0|%0, %1, 1}
+ vpextrq\t{$1, %1, %0|%0, %1, 1}
vpextrq\t{$1, %1, %0|%0, %1, 1}
%vmovhps\t{%1, %0|%0, %1}
psrldq\t{$8, %0|%0, 8}
@@ -20256,44 +20296,47 @@ (define_insn "*vec_extractv2di_1"
#"
[(set (attr "isa")
(cond [(eq_attr "alternative" "0")
- (const_string "x64_sse4")
+ (const_string "x64_sse4_noavx")
(eq_attr "alternative" "1")
+ (const_string "x64_avx")
+ (eq_attr "alternative" "2")
(const_string "x64_avx512dq")
- (eq_attr "alternative" "3")
- (const_string "sse2_noavx")
(eq_attr "alternative" "4")
- (const_string "avx")
+ (const_string "sse2_noavx")
(eq_attr "alternative" "5")
- (const_string "avx512bw")
+ (const_string "avx")
(eq_attr "alternative" "6")
- (const_string "noavx")
+ (const_string "avx512bw")
(eq_attr "alternative" "8")
+ (const_string "noavx")
+ (eq_attr "alternative" "9")
(const_string "x64")
]
(const_string "*")))
(set (attr "type")
- (cond [(eq_attr "alternative" "2,6,7")
+ (cond [(eq_attr "alternative" "3,7,8")
(const_string "ssemov")
- (eq_attr "alternative" "3,4,5")
+ (eq_attr "alternative" "4,5,6")
(const_string "sseishft1")
- (eq_attr "alternative" "8")
+ (eq_attr "alternative" "9")
(const_string "imov")
]
(const_string "sselog1")))
+ (set_attr "gpr32" "0,1,1,1,1,1,1,1,1,1")
(set (attr "length_immediate")
- (if_then_else (eq_attr "alternative" "0,1,3,4,5")
+ (if_then_else (eq_attr "alternative" "0,1,2,4,5,6")
(const_string "1")
(const_string "*")))
(set (attr "prefix_rex")
- (if_then_else (eq_attr "alternative" "0,1")
+ (if_then_else (eq_attr "alternative" "0")
(const_string "1")
(const_string "*")))
(set (attr "prefix_extra")
- (if_then_else (eq_attr "alternative" "0,1")
+ (if_then_else (eq_attr "alternative" "0")
(const_string "1")
(const_string "*")))
- (set_attr "prefix" "maybe_vex,evex,maybe_vex,orig,vex,evex,orig,*,*")
- (set_attr "mode" "TI,TI,V2SF,TI,TI,TI,V4SF,DI,DI")])
+ (set_attr "prefix" "orig,maybe_evex,evex,maybe_vex,orig,vex,evex,orig,*,*")
+ (set_attr "mode" "TI,TI,TI,V2SF,TI,TI,TI,V4SF,DI,DI")])
(define_split
[(set (match_operand:<ssescalarmode> 0 "register_operand")
@@ -20411,7 +20454,7 @@ (define_insn "*vec_concatv2si_sse4_1"
(match_operand:SI 1 "nonimmediate_operand"
" 0, 0, x,Yv, 0, 0,Yv,rm, 0,rm")
(match_operand:SI 2 "nonimm_or_0_operand"
- " rm,rm,rm,rm,Yr,*x,Yv, C,*ym, C")))]
+ " hBt,hBt,rm,rm,Yr,*x,Yv, C,*ym, C")))]
"TARGET_SSE4_1 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
"@
pinsrd\t{$1, %2, %0|%0, %2, 1}
@@ -20438,6 +20481,10 @@ (define_insn "*vec_concatv2si_sse4_1"
(const_string "mmxmov")
]
(const_string "sselog")))
+ (set (attr "gpr32")
+ (if_then_else (eq_attr "alternative" "0,1")
+ (const_string "0")
+ (const_string "1")))
(set (attr "prefix_extra")
(if_then_else (eq_attr "alternative" "0,1,2,3")
(const_string "1")
@@ -20562,7 +20609,7 @@ (define_insn "vec_concatv2di"
(match_operand:DI 1 "register_operand"
" 0, 0,x ,Yv,0,Yv,0,0,v")
(match_operand:DI 2 "nonimmediate_operand"
- " rm,rm,rm,rm,x,Yv,x,m,m")))]
+ " hm,hm,rm,rm,x,Yv,x,m,m")))]
"TARGET_SSE"
"@
pinsrq\t{$1, %2, %0|%0, %2, 1}
@@ -20592,6 +20639,10 @@ (define_insn "vec_concatv2di"
(eq_attr "alternative" "0,1,2,3,4,5")
(const_string "sselog")
(const_string "ssemov")))
+ (set (attr "gpr32")
+ (if_then_else (eq_attr "alternative" "0,1")
+ (const_string "0")
+ (const_string "1")))
(set (attr "prefix_rex")
(if_then_else (eq_attr "alternative" "0,1,2,3")
(const_string "1")
@@ -21525,7 +21576,7 @@ (define_insn "ssse3_pmaddubsw128"
(const_int 12) (const_int 14)])))
(sign_extend:V8HI
(vec_select:V8QI
- (match_operand:V16QI 2 "vector_operand" "xBm,Ywm")
+ (match_operand:V16QI 2 "vector_operand" "xBT,Ywm")
(parallel [(const_int 0) (const_int 2)
(const_int 4) (const_int 6)
(const_int 8) (const_int 10)
@@ -21548,6 +21599,7 @@ (define_insn "ssse3_pmaddubsw128"
pmaddubsw\t{%2, %0|%0, %2}
vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "type" "sseiadd")
(set_attr "atom_unit" "simul")
(set_attr "prefix_extra" "1")
@@ -21666,7 +21718,7 @@ (define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"
(sign_extend:<ssedoublemode>
(match_operand:VI2_AVX2_AVX512BW 1 "vector_operand"
"%0,<v_Yw>"))
(sign_extend:<ssedoublemode>
- (match_operand:VI2_AVX2_AVX512BW 2 "vector_operand"
"xBm,<v_Yw>m")))
+ (match_operand:VI2_AVX2_AVX512BW 2 "vector_operand"
"xBT,<v_Yw>m")))
(const_int 14))
(match_operand:VI2_AVX2_AVX512BW 3 "const1_operand"))
(const_int 1))))]
@@ -21676,6 +21728,7 @@ (define_insn "*<ssse3_avx2>_pmulhrsw<mode>3<mask_name>"
pmulhrsw\t{%2, %0|%0, %2}
vpmulhrsw\t{%2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2}"
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "type" "sseimul")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
@@ -21792,13 +21845,14 @@ (define_insn "<ssse3_avx2>_pshufb<mode>3<mask_name>"
[(set (match_operand:VI1_AVX512 0 "register_operand" "=x,<v_Yw>")
(unspec:VI1_AVX512
[(match_operand:VI1_AVX512 1 "register_operand" "0,<v_Yw>")
- (match_operand:VI1_AVX512 2 "vector_operand" "xBm,<v_Yw>m")]
+ (match_operand:VI1_AVX512 2 "vector_operand" "xBT,<v_Yw>m")]
UNSPEC_PSHUFB))]
"TARGET_SSSE3 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
"@
pshufb\t{%2, %0|%0, %2}
vpshufb\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
@@ -21915,7 +21969,7 @@ (define_insn "<ssse3_avx2>_palignr<mode>"
[(set (match_operand:VIMAX_AVX2_AVX512BW 0 "register_operand" "=x,<v_Yw>")
(unspec:VIMAX_AVX2_AVX512BW
[(match_operand:VIMAX_AVX2_AVX512BW 1 "register_operand" "0,<v_Yw>")
- (match_operand:VIMAX_AVX2_AVX512BW 2 "vector_operand" "xBm,<v_Yw>m")
+ (match_operand:VIMAX_AVX2_AVX512BW 2 "vector_operand" "xBT,<v_Yw>m")
(match_operand:SI 3 "const_0_to_255_mul_8_operand")]
UNSPEC_PALIGNR))]
"TARGET_SSSE3"
@@ -21933,6 +21987,7 @@ (define_insn "<ssse3_avx2>_palignr<mode>"
}
}
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "type" "sseishft")
(set_attr "atom_unit" "sishuf")
(set_attr "prefix_extra" "1")
@@ -22007,6 +22062,7 @@ (define_insn_and_split "ssse3_palignrdi"
}
[(set_attr "mmx_isa" "native,sse_noavx,avx")
(set_attr "type" "sseishft")
+ (set_attr "gpr32" "0,0,1")
(set_attr "atom_unit" "sishuf")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
@@ -22022,12 +22078,16 @@ (define_mode_iterator VI1248_AVX512VL_AVX512BW
(V8DI "TARGET_AVX512F") (V4DI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
(define_insn "*abs<mode>2"
- [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand" "=<v_Yw>")
+ [(set (match_operand:VI1248_AVX512VL_AVX512BW 0 "register_operand"
"=x,<v_Yw>")
(abs:VI1248_AVX512VL_AVX512BW
- (match_operand:VI1248_AVX512VL_AVX512BW 1 "vector_operand"
"<v_Yw>Bm")))]
+ (match_operand:VI1248_AVX512VL_AVX512BW 1 "vector_operand"
"xBT,<v_Yw>Bm")))]
"TARGET_SSSE3"
- "%vpabs<ssemodesuffix>\t{%1, %0|%0, %1}"
- [(set_attr "type" "sselog1")
+ "@
+ pabs<ssemodesuffix>\t{%1, %0|%0, %1}
+ vpabs<ssemodesuffix>\t{%1, %0|%0, %1}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
+ (set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "<sseinsnmode>")])
@@ -22365,11 +22425,15 @@ (define_mode_attr vi8_sse4_1_avx2_avx512
(define_insn "<vi8_sse4_1_avx2_avx512>_movntdqa"
[(set (match_operand:VI8_AVX2_AVX512F 0 "register_operand" "=Yr,*x,v")
- (unspec:VI8_AVX2_AVX512F [(match_operand:VI8_AVX2_AVX512F 1
"memory_operand" "m,m,m")]
+ (unspec:VI8_AVX2_AVX512F [(match_operand:VI8_AVX2_AVX512F 1
"memory_operand" "Bt,Bt,m")]
UNSPEC_MOVNTDQA))]
"TARGET_SSE4_1"
- "%vmovntdqa\t{%1, %0|%0, %1}"
+ "@
+ movntdqa\t{%1, %0|%0, %1}
+ movntdqa\t{%1, %0|%0, %1}
+ vmovntdqa\t{%1, %0|%0, %1}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
@@ -22388,6 +22452,7 @@ (define_insn "<sse4_1_avx2>_mpsadbw"
mpsadbw\t{%3, %2, %0|%0, %2, %3}
vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "sselog1")
(set_attr "gpr32" "0")
(set_attr "length_immediate" "1")
@@ -22401,7 +22466,7 @@ (define_insn "<sse4_1_avx2>_packusdw<mask_name>"
[(set (match_operand:VI2_AVX2_AVX512BW 0 "register_operand" "=Yr,*x,<v_Yw>")
(unspec:VI2_AVX2_AVX512BW
[(match_operand:<sseunpackmode> 1 "register_operand" "0,0,<v_Yw>")
- (match_operand:<sseunpackmode> 2 "vector_operand"
"YrBm,*xBm,<v_Yw>m")]
+ (match_operand:<sseunpackmode> 2 "vector_operand"
"YrBT,*xBT,<v_Yw>m")]
UNSPEC_US_TRUNCATE))]
"TARGET_SSE4_1 && <mask_mode512bit_condition> && <mask_avx512bw_condition>"
"@
@@ -22409,6 +22474,7 @@ (define_insn "<sse4_1_avx2>_packusdw<mask_name>"
packusdw\t{%2, %0|%0, %2}
vpackusdw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "sselog")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,<mask_prefix>")
@@ -22755,10 +22821,14 @@ (define_insn "sse4_1_<code>v8qiv8hi2<mask_name>"
(define_insn "*sse4_1_<code>v8qiv8hi2<mask_name>_1"
[(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,Yw")
(any_extend:V8HI
- (match_operand:V8QI 1 "memory_operand" "m,m,m")))]
+ (match_operand:V8QI 1 "memory_operand" "Bt,Bt,m")))]
"TARGET_SSE4_1 && <mask_avx512bw_condition> && <mask_avx512vl_condition>"
- "%vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ "@
+ pmov<extsuffix>bw\t{%1, %0|%0, %1}
+ pmov<extsuffix>bw\t{%1, %0|%0, %1}
+ vpmov<extsuffix>bw\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
@@ -22788,7 +22858,7 @@ (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_3"
[(set (match_operand:V16QI 0 "register_operand" "=Yr,*x,Yw")
(vec_select:V16QI
(vec_concat:V32QI
- (match_operand:V16QI 1 "vector_operand" "YrBm,*xBm,Ywm")
+ (match_operand:V16QI 1 "vector_operand" "YrBT,*xBT,Ywm")
(match_operand:V16QI 2 "const0_operand"))
(match_parallel 3 "pmovzx_parallel"
[(match_operand 4 "const_int_operand")])))]
@@ -22813,7 +22883,8 @@ (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_3"
DONE;
}
}
- [(set_attr "isa" "noavx,noavx,avx")])
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")])
(define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_4"
[(set (match_operand:V16QI 0 "register_operand" "=Yr,*x,Yw")
@@ -22821,7 +22892,7 @@ (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_4"
(vec_concat:V32QI
(subreg:V16QI
(vec_concat:VI248_128
- (match_operand:<ssehalfvecmode> 1 "vector_operand"
"YrBm,*xBm,Ywm")
+ (match_operand:<ssehalfvecmode> 1 "vector_operand"
"YrBT,*xBT,Ywm")
(match_operand:<ssehalfvecmode> 2 "const0_operand")) 0)
(match_operand:V16QI 3 "const0_operand"))
(match_parallel 4 "pmovzx_parallel"
@@ -22848,7 +22919,8 @@ (define_insn_and_split "*sse4_1_zero_extendv8qiv8hi2_4"
}
operands[1] = lowpart_subreg (V16QImode, operands[1], <ssehalfvecmode>mode);
}
- [(set_attr "isa" "noavx,noavx,avx")])
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")])
(define_expand "<insn>v8qiv8hi2"
[(set (match_operand:V8HI 0 "register_operand")
@@ -22967,10 +23039,11 @@ (define_insn "sse4_1_<code>v4qiv4si2<mask_name>"
(define_insn "*sse4_1_<code>v4qiv4si2<mask_name>_1"
[(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
(any_extend:V4SI
- (match_operand:V4QI 1 "memory_operand" "m,m,m")))]
+ (match_operand:V4QI 1 "memory_operand" "Bt,Bt,m")))]
"TARGET_SSE4_1 && <mask_avx512vl_condition>"
"%vpmov<extsuffix>bd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
@@ -23139,10 +23212,14 @@ (define_insn "sse4_1_<code>v4hiv4si2<mask_name>"
(define_insn "*sse4_1_<code>v4hiv4si2<mask_name>_1"
[(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
(any_extend:V4SI
- (match_operand:V4HI 1 "memory_operand" "m,m,m")))]
+ (match_operand:V4HI 1 "memory_operand" "Bt,Bt,m")))]
"TARGET_SSE4_1 && <mask_avx512vl_condition>"
- "%vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ "@
+ pmov<extsuffix>wd\t{%1, %0|%0, %1}
+ pmov<extsuffix>wd\t{%1, %0|%0, %1}
+ vpmov<extsuffix>wd\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
@@ -23191,7 +23268,7 @@ (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_3"
[(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
(vec_select:V8HI
(vec_concat:V16HI
- (match_operand:V8HI 1 "vector_operand" "YrBm,*xBm,vm")
+ (match_operand:V8HI 1 "vector_operand" "YrBT,*xBT,vm")
(match_operand:V8HI 2 "const0_operand"))
(match_parallel 3 "pmovzx_parallel"
[(match_operand 4 "const_int_operand")])))]
@@ -23214,7 +23291,8 @@ (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_3"
DONE;
}
}
- [(set_attr "isa" "noavx,noavx,avx")])
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")])
(define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_4"
[(set (match_operand:V8HI 0 "register_operand" "=Yr,*x,v")
@@ -23222,7 +23300,7 @@ (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_4"
(vec_concat:V16HI
(subreg:V8HI
(vec_concat:VI148_128
- (match_operand:<ssehalfvecmode> 1 "vector_operand"
"YrBm,*xBm,vm")
+ (match_operand:<ssehalfvecmode> 1 "vector_operand"
"YrBT,*xBT,vm")
(match_operand:<ssehalfvecmode> 2 "const0_operand")) 0)
(match_operand:V8HI 3 "const0_operand"))
(match_parallel 4 "pmovzx_parallel"
@@ -23247,7 +23325,8 @@ (define_insn_and_split "*sse4_1_zero_extendv4hiv4si2_4"
}
operands[1] = lowpart_subreg (V8HImode, operands[1], <ssehalfvecmode>mode);
}
- [(set_attr "isa" "noavx,noavx,avx")])
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")])
(define_insn "avx512f_<code>v8qiv8di2<mask_name>"
[(set (match_operand:V8DI 0 "register_operand" "=v")
@@ -23385,12 +23464,16 @@ (define_insn "sse4_1_<code>v2qiv2di2<mask_name>"
(set_attr "mode" "TI")])
(define_insn "*sse4_1_<code>v2qiv2di2<mask_name>_1"
- [(set (match_operand:V2DI 0 "register_operand" "=v")
+ [(set (match_operand:V2DI 0 "register_operand" "=x,v")
(any_extend:V2DI
- (match_operand:V2QI 1 "memory_operand" "m")))]
+ (match_operand:V2QI 1 "memory_operand" "Bt,m")))]
"TARGET_SSE4_1 && <mask_avx512vl_condition>"
- "%vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
- [(set_attr "type" "ssemov")
+ "@
+ pmov<extsuffix>bq\t{%1, %0|%0, %1}
+ vpmov<extsuffix>bq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
+ (set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "maybe_evex")
(set_attr "mode" "TI")])
@@ -23524,10 +23607,14 @@ (define_insn "sse4_1_<code>v2hiv2di2<mask_name>"
(define_insn "*sse4_1_<code>v2hiv2di2<mask_name>_1"
[(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v")
(any_extend:V2DI
- (match_operand:V2HI 1 "memory_operand" "m,m,m")))]
+ (match_operand:V2HI 1 "memory_operand" "Bt,Bt,m")))]
"TARGET_SSE4_1 && <mask_avx512vl_condition>"
- "%vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ "@
+ pmov<extsuffix>wq\t{%1, %0|%0, %1}
+ pmov<extsuffix>wq\t{%1, %0|%0, %1}
+ vpmov<extsuffix>wq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
@@ -23689,10 +23776,14 @@ (define_insn "sse4_1_<code>v2siv2di2<mask_name>"
(define_insn "*sse4_1_<code>v2siv2di2<mask_name>_1"
[(set (match_operand:V2DI 0 "register_operand" "=Yr,*x,v")
(any_extend:V2DI
- (match_operand:V2SI 1 "memory_operand" "m,m,m")))]
+ (match_operand:V2SI 1 "memory_operand" "Bt,Bt,m")))]
"TARGET_SSE4_1 && <mask_avx512vl_condition>"
- "%vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
+ "@
+ pmov<extsuffix>dq\t{%1, %0|%0, %1}
+ pmov<extsuffix>dq\t{%1, %0|%0, %1}
+ vpmov<extsuffix>dq\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}"
[(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")
(set_attr "type" "ssemov")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,orig,maybe_evex")
@@ -23719,7 +23810,7 @@ (define_insn_and_split "*sse4_1_zero_extendv2siv2di2_3"
[(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
(vec_select:V4SI
(vec_concat:V8SI
- (match_operand:V4SI 1 "vector_operand" "YrBm,*xBm,vm")
+ (match_operand:V4SI 1 "vector_operand" "YrBT,*xBT,vm")
(match_operand:V4SI 2 "const0_operand"))
(match_parallel 3 "pmovzx_parallel"
[(match_operand 4 "const_int_operand")])))]
@@ -23740,14 +23831,15 @@ (define_insn_and_split
"*sse4_1_zero_extendv2siv2di2_3"
DONE;
}
}
- [(set_attr "isa" "noavx,noavx,avx")])
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")])
(define_insn_and_split "*sse4_1_zero_extendv2siv2di2_4"
[(set (match_operand:V4SI 0 "register_operand" "=Yr,*x,v")
(vec_select:V4SI
(vec_concat:V8SI
(vec_concat:V4SI
- (match_operand:V2SI 1 "vector_operand" "YrBm, *xBm, vm")
+ (match_operand:V2SI 1 "vector_operand" "YrBT, *xBT, vm")
(match_operand:V2SI 2 "const0_operand"))
(match_operand:V4SI 3 "const0_operand"))
(match_parallel 4 "pmovzx_parallel"
@@ -23769,7 +23861,8 @@ (define_insn_and_split "*sse4_1_zero_extendv2siv2di2_4"
}
operands[1] = lowpart_subreg (V4SImode, operands[1], V2SImode);
}
- [(set_attr "isa" "noavx,noavx,avx")])
+ [(set_attr "isa" "noavx,noavx,avx")
+ (set_attr "gpr32" "0,0,1")])
(define_expand "<insn>v2siv2di2"
[(set (match_operand:V2DI 0 "register_operand")
@@ -25960,7 +26053,7 @@ (define_insn "xop_vpermil2<mode>3"
(define_insn "aesenc"
[(set (match_operand:V2DI 0 "register_operand" "=x,x,v")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v")
- (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")]
+ (match_operand:V2DI 2 "vector_operand" "xBT,xm,vm")]
UNSPEC_AESENC))]
"TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)"
"@
@@ -25969,6 +26062,7 @@ (define_insn "aesenc"
vaesenc\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,aes,avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "gpr32" "0,1,1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex,evex")
(set_attr "btver2_decode" "double,double,double")
@@ -25977,7 +26071,7 @@ (define_insn "aesenc"
(define_insn "aesenclast"
[(set (match_operand:V2DI 0 "register_operand" "=x,x,v")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v")
- (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")]
+ (match_operand:V2DI 2 "vector_operand" "xBT,xm,vm")]
UNSPEC_AESENCLAST))]
"TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)"
"@
@@ -25986,6 +26080,7 @@ (define_insn "aesenclast"
vaesenclast\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,aes,avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "gpr32" "0,1,1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex,evex")
(set_attr "btver2_decode" "double,double,double")
@@ -25994,7 +26089,7 @@ (define_insn "aesenclast"
(define_insn "aesdec"
[(set (match_operand:V2DI 0 "register_operand" "=x,x,v")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v")
- (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")]
+ (match_operand:V2DI 2 "vector_operand" "xBT,xm,vm")]
UNSPEC_AESDEC))]
"TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)"
"@
@@ -26003,6 +26098,7 @@ (define_insn "aesdec"
vaesdec\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,aes,avx512vl")
(set_attr "type" "sselog1")
+ (set_attr "gpr32" "0,1,1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex,evex")
(set_attr "btver2_decode" "double,double,double")
@@ -26011,7 +26107,7 @@ (define_insn "aesdec"
(define_insn "aesdeclast"
[(set (match_operand:V2DI 0 "register_operand" "=x,x,v")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v")
- (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")]
+ (match_operand:V2DI 2 "vector_operand" "xBT,xm,vm")]
UNSPEC_AESDECLAST))]
"TARGET_AES || (TARGET_VAES && TARGET_AVX512VL)"
"@
@@ -26019,6 +26115,7 @@ (define_insn "aesdeclast"
vaesdeclast\t{%2, %1, %0|%0, %1, %2}
vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "isa" "noavx,aes,avx512vl")
+ (set_attr "gpr32" "0,1,1")
(set_attr "type" "sselog1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,vex,evex")
@@ -26054,7 +26151,7 @@ (define_insn "aeskeygenassist"
(define_insn "pclmulqdq"
[(set (match_operand:V2DI 0 "register_operand" "=x,x,v")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x,v")
- (match_operand:V2DI 2 "vector_operand" "xBm,xm,vm")
+ (match_operand:V2DI 2 "vector_operand" "xBT,xm,vm")
(match_operand:SI 3 "const_0_to_255_operand")]
UNSPEC_PCLMUL))]
"TARGET_PCLMUL"
@@ -26064,6 +26161,7 @@ (define_insn "pclmulqdq"
vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
[(set_attr "isa" "noavx,avx,vpclmulqdqvl")
(set_attr "type" "sselog1")
+ (set_attr "gpr32" "0,1,1")
(set_attr "prefix_extra" "1")
(set_attr "length_immediate" "1")
(set_attr "prefix" "orig,vex,evex")
@@ -29395,7 +29493,7 @@ (define_insn "vgf2p8affineinvqb_<mode><mask_name>"
[(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v")
(unspec:VI1_AVX512F
[(match_operand:VI1_AVX512F 1 "register_operand" "0,v")
- (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")
+ (match_operand:VI1_AVX512F 2 "vector_operand" "xBT,vm")
(match_operand 3 "const_0_to_255_operand")]
UNSPEC_GF2P8AFFINEINV))]
"TARGET_GFNI"
@@ -29403,6 +29501,7 @@ (define_insn "vgf2p8affineinvqb_<mode><mask_name>"
gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3}
vgf2p8affineinvqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1,
%2, %3}"
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -29411,7 +29510,7 @@ (define_insn "vgf2p8affineqb_<mode><mask_name>"
[(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v")
(unspec:VI1_AVX512F
[(match_operand:VI1_AVX512F 1 "register_operand" "0,v")
- (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")
+ (match_operand:VI1_AVX512F 2 "vector_operand" "xBT,vm")
(match_operand 3 "const_0_to_255_operand")]
UNSPEC_GF2P8AFFINE))]
"TARGET_GFNI"
@@ -29419,6 +29518,7 @@ (define_insn "vgf2p8affineqb_<mode><mask_name>"
gf2p8affineqb\t{%3, %2, %0| %0, %2, %3}
vgf2p8affineqb\t{%3, %2, %1, %0<mask_operand4>| %0<mask_operand4>, %1, %2,
%3}"
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
@@ -29427,13 +29527,14 @@ (define_insn "vgf2p8mulb_<mode><mask_name>"
[(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,v")
(unspec:VI1_AVX512F
[(match_operand:VI1_AVX512F 1 "register_operand" "%0,v")
- (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")]
+ (match_operand:VI1_AVX512F 2 "vector_operand" "xBT,vm")]
UNSPEC_GF2P8MUL))]
"TARGET_GFNI"
"@
gf2p8mulb\t{%2, %0| %0, %2}
vgf2p8mulb\t{%2, %1, %0<mask_operand3>| %0<mask_operand3>, %1, %2}"
[(set_attr "isa" "noavx,avx")
+ (set_attr "gpr32" "0,1")
(set_attr "prefix_extra" "1")
(set_attr "prefix" "orig,maybe_evex")
(set_attr "mode" "<sseinsnmode>")])
--
2.31.1
