Hi Jeff,
> You might also peek at the RTL gcse/pre code which is also LCM based and
> has the same class of problems.
I found a similar approach to take care of this in gcse.cc/pre_edge_insert with
some comments as below.
/* We can't insert anything on an abnormal and
critical edge, so we insert the insn at the end of
the previous block. There are several alternatives
detailed in Morgans book P277 (sec 10.5) for
handling this situation. This one is easiest for
now. */
if (eg->flags & EDGE_ABNORMAL)
insert_insn_end_basic_block (index_map[j], bb);
else
{
insn = process_insert_insn (index_map[j]);
insert_insn_on_edge (insn, eg);
}
It looks the insert_insn_end_basic_block is designed to handle the ABNORMAL
edge by inserting at end of previous block from the comments.
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel....@gcc.gnu.org> On Behalf
Of Li, Pan2 via Gcc-patches
Sent: Thursday, August 24, 2023 12:54 PM
To: Jeff Law <jeffreya...@gmail.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang <yanzhang.w...@intel.com>;
kito.ch...@gmail.com
Subject: RE: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook
Thanks Jeff.
> That implies a save/restore pair around the call (possibly optimized so
> that we minimize the number of save/restores). I would have expected
> x86 to already be doing this. But maybe there's some ABI thing around
> mmx vs x86 state that allows it to be avoided....
Very similar to save/restore but optional.
If no static rounding mode instrinsic here, it is unnecessary to add
save/restore
pair around the call. I bet mode-switching take care of this already.
Pan
-----Original Message-----
From: Jeff Law <jeffreya...@gmail.com>
Sent: Thursday, August 24, 2023 7:27 AM
To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org
Cc: juzhe.zh...@rivai.ai; Wang, Yanzhang <yanzhang.w...@intel.com>;
kito.ch...@gmail.com
Subject: Re: [PATCH v1] Mode-Switching: Add optional EMIT_AFTER hook
On 8/23/23 08:54, Li, Pan2 wrote:
> Thanks Jeff for comments.
>
>> Understood. So the natural question is why does x86/sh not need this
>> for its mode switching? Don't all the same issues exist on those
>> targets as well?
>
> AFAIK, it comes from the different design principle between the risc-v and
> x86/arm intrinsic API.
> The risc-v rvv FP rounding mode intrinsic API has one abstract level above
> the insn itself, while
> the x86/arm only indicates the semantics of the insn.
>
> For example, if one vector instruction VFADD doesn't have static rounding
> mode (aka encoding rm in insn),
> there is no such a intrinsic API contains rounding mode argument in x86/arm.
> While the risc-v fp
> vector intrinsic will always have static rounding mode API if the frm is
> honored.
>
> In short, the risc-v intrinsic API is closer to the end-user, while the
> x86/arm instrinsic API is closer to insn itself.
OK, but I'm still strugging to see how the distinction is important
here. Ultimately there's a state at a call site. We need to make sure
that state from the current function doesn't impact the callee and we
need to make sure that the callee doesn't impact the state in the caller.
That implies a save/restore pair around the call (possibly optimized so
that we minimize the number of save/restores). I would have expected
x86 to already be doing this. But maybe there's some ABI thing around
mmx vs x86 state that allows it to be avoided....
>
> For the rest part, will have a try based on your suggestion soon as I am in
> the middle of something.
No problem. Get to it when you can. I think it affects you more than
me :-)
jeff
