Re: [PATCH] RISC-V: Support simplify (-1-x) for vector.

[Jeff Law via Gcc-patches]

On 8/16/23 02:40, yanzhang.wang--- via Gcc-patches wrote:
From: Yanzhang Wang <yanzhang.w...@intel.com>

The pattern is enabled for scalar but not for vector. The patch try to
make it consistent and will convert below code,

shortcut_for_riscv_vrsub_case_1_32:
         vl1re32.v       v1,0(a1)
         vsetvli zero,a2,e32,m1,ta,ma
         vrsub.vi        v1,v1,-1
         vs1r.v  v1,0(a0)
         ret

to,

shortcut_for_riscv_vrsub_case_1_32:
         vl1re32.v       v1,0(a1)
         vsetvli zero,a2,e32,m1,ta,ma
         vnot.v  v1,v1
         vs1r.v  v1,0(a0)
         ret

gcc/ChangeLog:

        * simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
     Get -1 with mode.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/simplify-vrsub.c: New test.
Just a note.  It is customary to indicate what testing you did for each 
patch.  A patch which changes target independent code should be 
bootstrapped and regression tested on at least one major target (most 
folks use x86_64 or aarch64).

If you change target code it is customary to run the testsuite on that 
target.  Ideally that would include a bootstrap and regression test, but 
that's not always possible (cross compilers) in which case you just 
build the toolchain and run the cross tests.

I went ahead and bootstrapped & regression tested this on 
x86_64-linux-gnu where it passed without regressions.

I'll push this to the trunk.

Thanks,
jeff