From: Pan Li <pan2...@intel.com>
This patch would like to support the rounding mode API for the
VFNCVT.XU.F.W as the below samples.
* __riscv_vfncvt_xu_f_w_u16mf2_rm
* __riscv_vfncvt_xu_f_w_u16mf2_rm_m
Signed-off-by: Pan Li <pan2...@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(vfncvt_xu_frm_obj): New declaration.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfncvt_xu_frm): New intrinsic function def.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-ncvt-xu.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/rvv/base/float-point-ncvt-xu.c | 29 +++++++++++++++++++
4 files changed, 33 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 2f40eeaeda5..acadec2afca 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2509,6 +2509,7 @@ static CONSTEXPR const vfwcvt_f vfwcvt_f_obj;
static CONSTEXPR const vfncvt_x<UNSPEC_VFCVT> vfncvt_x_obj;
static CONSTEXPR const vfncvt_x<UNSPEC_VFCVT, HAS_FRM> vfncvt_x_frm_obj;
static CONSTEXPR const vfncvt_x<UNSPEC_UNSIGNED_VFCVT> vfncvt_xu_obj;
+static CONSTEXPR const vfncvt_x<UNSPEC_UNSIGNED_VFCVT, HAS_FRM>
vfncvt_xu_frm_obj;
static CONSTEXPR const vfncvt_rtz_x<FIX> vfncvt_rtz_x_obj;
static CONSTEXPR const vfncvt_rtz_x<UNSIGNED_FIX> vfncvt_rtz_xu_obj;
static CONSTEXPR const vfncvt_f vfncvt_f_obj;
@@ -2764,6 +2765,7 @@ BASE (vfwcvt_f)
BASE (vfncvt_x)
BASE (vfncvt_x_frm)
BASE (vfncvt_xu)
+BASE (vfncvt_xu_frm)
BASE (vfncvt_rtz_x)
BASE (vfncvt_rtz_xu)
BASE (vfncvt_f)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index edff0de2715..9bd09a41960 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -222,6 +222,7 @@ extern const function_base *const vfwcvt_f;
extern const function_base *const vfncvt_x;
extern const function_base *const vfncvt_x_frm;
extern const function_base *const vfncvt_xu;
+extern const function_base *const vfncvt_xu_frm;
extern const function_base *const vfncvt_rtz_x;
extern const function_base *const vfncvt_rtz_xu;
extern const function_base *const vfncvt_f;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 5e37bae318a..1e0e989fc2a 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -473,6 +473,7 @@ DEF_RVV_FUNCTION (vfncvt_f, narrow_alu, full_preds,
f_to_nf_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_rod_f, narrow_alu, full_preds, f_to_nf_f_w_ops)
DEF_RVV_FUNCTION (vfncvt_x_frm, narrow_alu_frm, full_preds, f_to_ni_f_w_ops)
+DEF_RVV_FUNCTION (vfncvt_xu_frm, narrow_alu_frm, full_preds, f_to_nu_f_w_ops)
/* 14. Vector Reduction Operations. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
new file mode 100644
index 00000000000..82c3e1364bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-ncvt-xu.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vuint16mf2_t
+test_riscv_vfncvt_xu_f_w_u16mf2_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfncvt_xu_f_w_u16mf2_rm (op1, 0, vl);
+}
+
+vuint16mf2_t
+test_vfncvt_xu_f_w_u16mf2_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfncvt_xu_f_w_u16mf2_rm_m (mask, op1, 1, vl);
+}
+
+vuint16mf2_t
+test_riscv_vfncvt_xu_f_w_u16mf2 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfncvt_xu_f_w_u16mf2 (op1, vl);
+}
+
+vuint16mf2_t
+test_vfncvt_xu_f_w_u16mf2_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfncvt_xu_f_w_u16mf2_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfncvt\.xu\.f\.w\s+v[0-9]+,\s*v[0-9]+} 4
} } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
