From: Pan Li <pan2...@intel.com>
This patch would like to support the rounding mode API for the
VFCVT.XU.F.V as the below samples.
* __riscv_vfcvt_xu_f_v_u32m1_rm
* __riscv_vfcvt_xu_f_v_u32m1_rm_m
Signed-off-by: Pan Li <pan2...@intel.com>
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc
(BASE): New declaration.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def
(vfcvt_xu_frm): New intrinsic function def..
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/float-point-cvt-xu.c: New test.
---
.../riscv/riscv-vector-builtins-bases.cc | 2 ++
.../riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 1 +
.../riscv/rvv/base/float-point-cvt-xu.c | 29 +++++++++++++++++++
4 files changed, 33 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index 817d2ed016a..421f4096db8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -2478,6 +2478,7 @@ static CONSTEXPR const vmv_v vfmv_v_obj;
static CONSTEXPR const vfcvt_x<UNSPEC_VFCVT> vfcvt_x_obj;
static CONSTEXPR const vfcvt_x<UNSPEC_VFCVT, HAS_FRM> vfcvt_x_frm_obj;
static CONSTEXPR const vfcvt_x<UNSPEC_UNSIGNED_VFCVT> vfcvt_xu_obj;
+static CONSTEXPR const vfcvt_x<UNSPEC_UNSIGNED_VFCVT, HAS_FRM>
vfcvt_xu_frm_obj;
static CONSTEXPR const vfcvt_rtz_x<FIX> vfcvt_rtz_x_obj;
static CONSTEXPR const vfcvt_rtz_x<UNSIGNED_FIX> vfcvt_rtz_xu_obj;
static CONSTEXPR const vfcvt_f vfcvt_f_obj;
@@ -2728,6 +2729,7 @@ BASE (vfmv_v)
BASE (vfcvt_x)
BASE (vfcvt_x_frm)
BASE (vfcvt_xu)
+BASE (vfcvt_xu_frm)
BASE (vfcvt_rtz_x)
BASE (vfcvt_rtz_xu)
BASE (vfcvt_f)
diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
b/gcc/config/riscv/riscv-vector-builtins-bases.h
index 50a7d7ffb6f..98b61655692 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.h
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
@@ -207,6 +207,7 @@ extern const function_base *const vfmv_v;
extern const function_base *const vfcvt_x;
extern const function_base *const vfcvt_x_frm;
extern const function_base *const vfcvt_xu;
+extern const function_base *const vfcvt_xu_frm;
extern const function_base *const vfcvt_rtz_x;
extern const function_base *const vfcvt_rtz_xu;
extern const function_base *const vfcvt_f;
diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
b/gcc/config/riscv/riscv-vector-builtins-functions.def
index 8b6a7cc49f3..613bbe7a855 100644
--- a/gcc/config/riscv/riscv-vector-builtins-functions.def
+++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
@@ -446,6 +446,7 @@ DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, i_to_f_x_v_ops)
DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds, u_to_f_xu_v_ops)
DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
+DEF_RVV_FUNCTION (vfcvt_xu_frm, alu_frm, full_preds, f_to_u_f_v_ops)
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
new file mode 100644
index 00000000000..bb164b2b001
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-xu.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+vuint32m1_t
+test_riscv_vfcvt_xu_f_v_u32m1_rm (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1_rm (op1, 0, vl);
+}
+
+vuint32m1_t
+test_vfcvt_xu_f_v_u32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1_rm_m (mask, op1, 1, vl);
+}
+
+vuint32m1_t
+test_riscv_vfcvt_xu_f_vv_u32m1 (vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1 (op1, vl);
+}
+
+vuint32m1_t
+test_vfcvt_xu_f_v_u32m1_m (vbool32_t mask, vfloat32m1_t op1, size_t vl) {
+ return __riscv_vfcvt_xu_f_v_u32m1_m (mask, op1, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfcvt\.xu\.f\.v\s+v[0-9]+,\s*v[0-9]+} 4
} } */
+/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */
--
2.34.1
