Committed as passed both the bootstrap and regression test in x86, thanks Jeff.
Pan -----Original Message----- From: Jeff Law <jeffreya...@gmail.com> Sent: Tuesday, August 15, 2023 1:21 AM To: Li, Pan2 <pan2...@intel.com>; gcc-patches@gcc.gnu.org Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang <yanzhang.w...@intel.com> Subject: Re: [PATCH v4] Mode-Switching: Fix SET_SRC ICE for create_pre_exit On 8/12/23 18:56, pan2...@intel.com wrote: > From: Pan Li <pan2...@intel.com> > > In same cases, like gcc/testsuite/gcc.dg/pr78148.c in RISC-V, there will > be only 1 operand when SET_SRC in create_pre_exit. For example as below. > > (insn 13 9 14 2 (clobber (reg/i:TI 10 a0)) > "gcc/testsuite/gcc.dg/pr78148.c":24:1 -1 > (expr_list:REG_UNUSED (reg/i:TI 10 a0) > (nil))) > > Unfortunately, SET_SRC requires at least 2 operands and then Segment > Fault here. For SH4 part result in Segment Fault, it looks like only > valid when the return_copy_pat is load or something like that. Thus, > this patch try to fix it by restrict the SET insn for SET_SRC. > > Signed-off-by: Pan Li <pan2...@intel.com> > > gcc/ChangeLog: > > * mode-switching.cc (create_pre_exit): Add SET insn check. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/mode-switch-ice-1.c: New test. OK. Thanks for the updated version. jeff
