Committed, thanks Juzhe. Pan
From: juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> Sent: Monday, August 14, 2023 9:04 AM To: Li, Pan2 <pan2...@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> Cc: Li, Pan2 <pan2...@intel.com>; Wang, Yanzhang <yanzhang.w...@intel.com>; kito.cheng <kito.ch...@gmail.com> Subject: Re: [PATCH v1] RISC-V: Support RVV VFWMACC rounding mode intrinsic API LGTm ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: pan2.li<mailto:pan2...@intel.com> Date: 2023-08-13 16:02 To: gcc-patches<mailto:gcc-patches@gcc.gnu.org> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; pan2.li<mailto:pan2...@intel.com>; yanzhang.wang<mailto:yanzhang.w...@intel.com>; kito.cheng<mailto:kito.ch...@gmail.com> Subject: [PATCH v1] RISC-V: Support RVV VFWMACC rounding mode intrinsic API From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> This patch would like to support the rounding mode API for the VFWMACC as the below samples. * __riscv_vfwmacc_vv_f64m2_rm * __riscv_vfwmacc_vv_f64m2_rm_m * __riscv_vfwmacc_vf_f64m2_rm * __riscv_vfwmacc_vf_f64m2_rm_m Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (class vfwmacc_frm): New class for vfwmacc frm. (vfwmacc_frm_obj): New declaration. (BASE): Ditto. * config/riscv/riscv-vector-builtins-bases.h: Ditto. * config/riscv/riscv-vector-builtins-functions.def (vfwmacc_frm): Function definition for vfwmacc. * config/riscv/riscv-vector-builtins.cc (function_expander::use_widen_ternop_insn): Add frm support. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-fwmacc.c: New test. --- .../riscv/riscv-vector-builtins-bases.cc | 25 ++++++++++ .../riscv/riscv-vector-builtins-bases.h | 1 + .../riscv/riscv-vector-builtins-functions.def | 3 ++ gcc/config/riscv/riscv-vector-builtins.cc | 22 +++++++-- .../riscv/rvv/base/float-point-fwmacc.c | 47 +++++++++++++++++++ 5 files changed, 93 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index e14e9aa7809..e84d6d1d047 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -539,6 +539,29 @@ public: } }; +/* Implements below instructions for frm + - vfwmacc +*/ +class vfwmacc_frm : public function_base +{ +public: + bool has_rounding_mode_operand_p () const override { return true; } + + bool has_merge_operand_p () const override { return false; } + + rtx expand (function_expander &e) const override + { + if (e.op_info->op == OP_TYPE_vf) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul_scalar (PLUS, e.vector_mode ())); + if (e.op_info->op == OP_TYPE_vv) + return e.use_widen_ternop_insn ( + code_for_pred_widen_mul (PLUS, e.vector_mode ())); + + gcc_unreachable (); + } +}; + /* Implements vrsub. */ class vrsub : public function_base { @@ -2315,6 +2338,7 @@ static CONSTEXPR const vfnmadd_frm vfnmadd_frm_obj; static CONSTEXPR const vfmsub vfmsub_obj; static CONSTEXPR const vfmsub_frm vfmsub_frm_obj; static CONSTEXPR const vfwmacc vfwmacc_obj; +static CONSTEXPR const vfwmacc_frm vfwmacc_frm_obj; static CONSTEXPR const vfwnmacc vfwnmacc_obj; static CONSTEXPR const vfwmsac vfwmsac_obj; static CONSTEXPR const vfwnmsac vfwnmsac_obj; @@ -2558,6 +2582,7 @@ BASE (vfnmadd_frm) BASE (vfmsub) BASE (vfmsub_frm) BASE (vfwmacc) +BASE (vfwmacc_frm) BASE (vfwnmacc) BASE (vfwmsac) BASE (vfwnmsac) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index e60cebab4ae..acbc7d42fbe 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -176,6 +176,7 @@ extern const function_base *const vfnmadd_frm; extern const function_base *const vfmsub; extern const function_base *const vfmsub_frm; extern const function_base *const vfwmacc; +extern const function_base *const vfwmacc_frm; extern const function_base *const vfwnmacc; extern const function_base *const vfwmsac; extern const function_base *const vfwnmsac; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index d75b281eebe..0b73a5bcbc5 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -376,6 +376,9 @@ DEF_RVV_FUNCTION (vfwmsac, alu, full_preds, f_wwfv_ops) DEF_RVV_FUNCTION (vfwnmsac, alu, full_preds, f_wwvv_ops) DEF_RVV_FUNCTION (vfwnmsac, alu, full_preds, f_wwfv_ops) +DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwvv_ops) +DEF_RVV_FUNCTION (vfwmacc_frm, alu_frm, full_preds, f_wwfv_ops) + // 13.8. Vector Floating-Point Square-Root Instruction DEF_RVV_FUNCTION (vfsqrt, alu, full_preds, f_v_ops) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index abab06c00ed..ad4a9098620 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3771,17 +3771,29 @@ function_expander::use_widen_ternop_insn (insn_code icode) add_all_one_mask_operand (mask_mode ()); for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++) - add_input_operand (argno); + { + if (base->has_rounding_mode_operand_p () + && argno == call_expr_nargs (exp) - 2) + { + /* Since the rounding mode argument position is not consistent with + the instruction pattern, we need to skip rounding mode argument + here. */ + continue; + } + add_input_operand (argno); + } add_input_operand (Pmode, get_tail_policy_for_pred (pred)); add_input_operand (Pmode, get_mask_policy_for_pred (pred)); add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX)); - /* TODO: Currently, we don't support intrinsic that is modeling rounding mode. - We add default rounding mode for the intrinsics that didn't model rounding - mode yet. */ + if (base->has_rounding_mode_operand_p ()) + add_input_operand (call_expr_nargs (exp) - 2); + + /* The RVV floating-point only support dynamic rounding mode in the + FRM register. */ if (opno != insn_data[icode].n_generator_args) - add_input_operand (Pmode, const0_rtx); + add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode)); return generate_insn (icode); } diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c new file mode 100644 index 00000000000..45bb628fa7b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-fwmacc.c @@ -0,0 +1,47 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat64m2_t +test_vfwmacc_vv_f32m1_rm (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwmacc_vv_f64m2_rm (vd, op1, op2, 0, vl); +} + +vfloat64m2_t +test_vfwmacc_vv_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwmacc_vv_f64m2_rm_m (mask, vd, op1, op2, 1, vl); +} + +vfloat64m2_t +test_vfwmacc_vf_f32m1_rm (vfloat64m2_t vd, float32_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwmacc_vf_f64m2_rm (vd, op1, op2, 2, vl); +} + +vfloat64m2_t +test_vfwmacc_vf_f32m1_rm_m (vbool32_t mask, vfloat64m2_t vd, float32_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwmacc_vf_f64m2_rm_m (mask, vd, op1, op2, 3, vl); +} + +vfloat64m2_t +test_vfwmacc_vv_f32m1 (vfloat64m2_t vd, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfwmacc_vv_f64m2 (vd, op1, op2, vl); +} + +vfloat64m2_t +test_vfwmacc_vv_f32m1_m (vbool32_t mask, vfloat64m2_t vd, vfloat32m1_t op1, + vfloat32m1_t op2, size_t vl) { + return __riscv_vfwmacc_vv_f64m2_m (mask, vd, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfwmacc\.[vw][vf]\s+v[0-9]+,\s*[fav]+[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */ -- 2.34.1
