Thanks so much for Kito's online and offline comments.
I have upload V2 patchs which address all comments.


https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626935.html


Best,
Lehua




------------------ Original ------------------
From:                                                                           
                                             "Kito Cheng"                       
                                                             
<kito.ch...@gmail.com&gt;;
Date:&nbsp;Mon, Aug 7, 2023 04:51 PM
To:&nbsp;"Lehua Ding"<lehua.d...@rivai.ai&gt;;
Cc:&nbsp;"gcc-patches"<gcc-patches@gcc.gnu.org&gt;;"juzhe.zhong"<juzhe.zh...@rivai.ai&gt;;"rdapp.gcc"<rdapp....@gmail.com&gt;;"palmer"<pal...@rivosinc.com&gt;;"jeffreyalaw"<jeffreya...@gmail.com&gt;;
Subject:&nbsp;Re: [PATCH 1/3] RISC-V: Part-1: Select suitable vector registers 
for vector type args and returns



Thanks for the high quality patch, it's generally LGTM, only a few
minor comments :)

&gt; +&nbsp; /* The number and alignment of vector registers need for this 
scalable vector
&gt; +&nbsp;&nbsp;&nbsp;&nbsp; argument. When the mode size is less than a full 
vector, we use 1 vector
&gt; +&nbsp;&nbsp;&nbsp;&nbsp; register to pass. Just call 
TARGET_HARD_REGNO_NREGS for the number
&gt; +&nbsp;&nbsp;&nbsp;&nbsp; infomation.&nbsp; */

gmail told me here is a typo: information :P

&gt; +&nbsp; int nregs = riscv_hard_regno_nregs (V_ARG_FIRST, mode);
&gt; +&nbsp; int LMUL = riscv_v_ext_tuple_mode_p (mode)
&gt; 
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
? nregs / riscv_vector::get_nf (mode)
&gt; 
+&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
: nregs;
&gt; +&nbsp; int arg_reg_start = V_ARG_FIRST - V_REG_FIRST;
&gt; +&nbsp; int arg_reg_end = V_ARG_LAST - V_REG_FIRST;
&gt; +&nbsp; int aligned_reg_start = (arg_reg_start + LMUL - 1) &amp; -LMUL;

Use` ROUND_UP (arg_reg_start, LMUL)`

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