Thanks so much for Kito's online and offline comments. I have upload V2 patchs which address all comments.
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/626935.html Best, Lehua ------------------ Original ------------------ From: "Kito Cheng" <kito.ch...@gmail.com>; Date: Mon, Aug 7, 2023 04:51 PM To: "Lehua Ding"<lehua.d...@rivai.ai>; Cc: "gcc-patches"<gcc-patches@gcc.gnu.org>;"juzhe.zhong"<juzhe.zh...@rivai.ai>;"rdapp.gcc"<rdapp....@gmail.com>;"palmer"<pal...@rivosinc.com>;"jeffreyalaw"<jeffreya...@gmail.com>; Subject: Re: [PATCH 1/3] RISC-V: Part-1: Select suitable vector registers for vector type args and returns Thanks for the high quality patch, it's generally LGTM, only a few minor comments :) > + /* The number and alignment of vector registers need for this scalable vector > + argument. When the mode size is less than a full vector, we use 1 vector > + register to pass. Just call TARGET_HARD_REGNO_NREGS for the number > + infomation. */ gmail told me here is a typo: information :P > + int nregs = riscv_hard_regno_nregs (V_ARG_FIRST, mode); > + int LMUL = riscv_v_ext_tuple_mode_p (mode) > + ? nregs / riscv_vector::get_nf (mode) > + : nregs; > + int arg_reg_start = V_ARG_FIRST - V_REG_FIRST; > + int arg_reg_end = V_ARG_LAST - V_REG_FIRST; > + int aligned_reg_start = (arg_reg_start + LMUL - 1) & -LMUL; Use` ROUND_UP (arg_reg_start, LMUL)`