[PATCH] RISC-V: Support NPATTERNS = 1 stepped vector[PR110950]

[Juzhe-Zhong]

This patch fix ICE: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110950

0x1cf8939 expand_const_vector
        ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:1587

        PR target/110950

gcc/ChangeLog:

        * config/riscv/riscv-v.cc (expand_const_vector): Add NPATTERNS = 1 
stepped vector support.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/pr110950.c: New test.

---
 gcc/config/riscv/riscv-v.cc                   | 19 +++++++++++++++++++
 .../gcc.target/riscv/rvv/autovec/pr110950.c   | 12 ++++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index a7b2d7dd2fe..0bea04c1967 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1563,6 +1563,25 @@ expand_const_vector (rtx target, rtx src)
                               add_ops);
            }
        }
+      else if (npatterns == 1 && nelts_per_pattern == 3)
+       {
+         /* Generate the following CONST_VECTOR:
+            { base0, base1, base1 + step, base1 + step * 2, ... }  */
+         rtx base0 = CONST_VECTOR_ELT (src, 0);
+         rtx base1 = CONST_VECTOR_ELT (src, 1);
+         rtx step = CONST_VECTOR_ELT (src, 2);
+         /* Step 1 - { base1, base1 + step, base1 + step * 2, ... }  */
+         rtx tmp = gen_reg_rtx (mode);
+         emit_insn (gen_vec_series (mode, tmp, base1, step));
+         /* Step 2 - { base0, base1, base1 + step, base1 + step * 2, ... }  */
+         scalar_mode elem_mode = GET_MODE_INNER (mode);
+         if (!rtx_equal_p (base0, const0_rtx))
+           base0 = force_reg (elem_mode, base0);
+
+         insn_code icode = optab_handler (vec_shl_insert_optab, mode);
+         gcc_assert (icode != CODE_FOR_nothing);
+         emit_insn (GEN_FCN (icode) (target, tmp, base0));
+       }
       else
        /* TODO: We will enable more variable-length vector in the future.  */
        gcc_unreachable ();
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c
new file mode 100644
index 00000000000..9f276d06338
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110950.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d 
--param=riscv-autovec-preference=scalable -Ofast" } */
+
+int a;
+void b() {
+  long *c = 0;
+  int *d;
+  for (; a; ++a)
+    c[a] = d[-a];
+}
+
+/* { dg-final { scan-assembler-times {vslide1up\.vx} 1 } } */
-- 
2.36.3