On 8/8/23 15:52, Maciej W. Rozycki wrote:
On Fri, 4 Aug 2023, Jeff Law via Gcc-patches wrote:
It's also something I kept meaning to resolve and your submission just gave me
the proper motivation to move zicond forward. The target specific bits you
did lined up perfectly with the community feedback on the original VRULL
implementation as well as the direction Ventana had taken on our internal
tree.
I wonder however why do we need so much more code, including the middle
end too, to support this ISA extension than we do for the very same set of
MIPSr6 instructions under ISA_HAS_SEL, hmm...
Because it doesn't handle as many cases as we're handling in the RISC-V
port.
I'd bet if you take Xiao's testcases and run them on a mips cross many,
if not most, won't optimize down into the mips equivalents.
One such example would be
(set (target)
(if_then_else (eq (reg A) (const_int 0))
(reg A)
(reg B)))
This is just one example obviously, but there are others.
jeff
