Committed, thanks Robin.
Pan
-----Original Message-----
From: Gcc-patches <gcc-patches-bounces+pan2.li=intel....@gcc.gnu.org> On Behalf
Of ???
Sent: Tuesday, August 8, 2023 5:15 AM
To: rdapp.gcc <rdapp....@gmail.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: rdapp.gcc <rdapp....@gmail.com>; kito.cheng <kito.ch...@gmail.com>;
kito.cheng <kito.ch...@sifive.com>; Jeff Law <jeffreya...@gmail.com>
Subject: Re: Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
Thanks Robin.
Yes, we should not allow vsetvli rd,rs1 which is generated by SELECT_VL for
partial vector auto-vectorzation.
But I believe scan-assembler-not csrr is enough.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-08-08 03:46
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw
Subject: Re: [PATCH] RISC-V: Support VLS basic operation auto-vectorization
Hi Juzhe,
thanks, looks good from my side.
> +/* { dg-final { scan-assembler-times {vand\.vi\s+v[0-9]+,\s*v[0-9]+,\s*-16}
> 42 } } */
> +/* { dg-final { scan-assembler-not {csrr} } } */
I was actually looking for a scan-assembler-not vsetvli... but the
csrr will do as well.
Regards
Robin
