In loongarch32 target, conversions between SF/DF and DI are not supported. gcc/ChangeLog:
* config/loongarch/loongarch.md: Check TARGET_64BIT in insns regarding SF/DF <-> DI conversion. --- gcc/config/loongarch/loongarch.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index c611a8a822a..bced4b08569 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1504,7 +1504,7 @@ (define_insn "floatdidf2" [(set (match_operand:DF 0 "register_operand" "=f") (float:DF (match_operand:DI 1 "register_operand" "f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" "ffint.d.l\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "DF") @@ -1522,7 +1522,7 @@ (define_insn "floatdisf2" [(set (match_operand:SF 0 "register_operand" "=f") (float:SF (match_operand:DI 1 "register_operand" "f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" "ffint.s.l\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "SF") @@ -1576,7 +1576,7 @@ (define_expand "fixuns_truncdfdi2" [(set (match_operand:DI 0 "register_operand") (unsigned_fix:DI (match_operand:DF 1 "register_operand")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" { rtx reg1 = gen_reg_rtx (DFmode); rtx reg2 = gen_reg_rtx (DFmode); @@ -1658,7 +1658,7 @@ (define_expand "fixuns_truncsfdi2" [(set (match_operand:DI 0 "register_operand") (unsigned_fix:DI (match_operand:SF 1 "register_operand")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT && TARGET_64BIT" { rtx reg1 = gen_reg_rtx (SFmode); rtx reg2 = gen_reg_rtx (SFmode); -- 2.41.0