I saw you didn't push yet, so I pushed another patch to fix those
unused variable issues.
On Mon, Jul 31, 2023 at 9:12 PM Kito Cheng <kito.ch...@sifive.com> wrote:
>
> Ooops, I guess my code base was too old, and forgot to check that after
> rebase, thanks for fix that!
>
> Juzhe-Zhong <juzhe.zh...@rivai.ai>於 2023年7月31日 週一，20:21寫道：
>>
>> Fix bugs:
>> ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc: In function ‘void
>> riscv_vector::emit_vlmax_masked_fp_mu_insn(unsigned int, int, rtx_def**)’:
>> ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:999:54: error: request for
>> member ‘require’ in ‘riscv_vector::get_mask_mode(dest_mode)’, which is of
>> non-class type ‘machine_mode’
>> machine_mode mask_mode = get_mask_mode (dest_mode).require ();
>> ^~~~~~~
>> ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc: In function ‘void
>> riscv_vector::emit_nonvlmax_tumu_insn(unsigned int, int, rtx_def**, rtx)’:
>> ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:1057:54: error: request for
>> member ‘require’ in ‘riscv_vector::get_mask_mode(dest_mode)’, which is of
>> non-class type ‘machine_mode’
>> machine_mode mask_mode = get_mask_mode (dest_mode).require ();
>> ^~~~~~~
>> ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc: In function ‘void
>> riscv_vector::emit_nonvlmax_fp_tumu_insn(unsigned int, int, rtx_def**, rtx)’:
>> ../../../riscv-gcc/gcc/config/riscv/riscv-v.cc:1076:54: error: request for
>> member ‘require’ in ‘riscv_vector::get_mask_mode(dest_mode)’, which is of
>> non-class type ‘machine_mode’
>> machine_mode mask_mode = get_mask_mode (dest_mode).require ();
>>
>> Obvious fix. Pushed.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv-v.cc (emit_vlmax_masked_fp_mu_insn): Fix bug.
>> (emit_nonvlmax_tumu_insn): Ditto.
>> (emit_nonvlmax_fp_tumu_insn): Ditto.
>> (expand_vec_series): Ditto.
>> (expand_vector_init_insert_elems): Ditto.
>>
>> ---
>> gcc/config/riscv/riscv-v.cc | 8 +++-----
>> 1 file changed, 3 insertions(+), 5 deletions(-)
>>
>> diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
>> index 76b437cc55e..40e4574dcc0 100644
>> --- a/gcc/config/riscv/riscv-v.cc
>> +++ b/gcc/config/riscv/riscv-v.cc
>> @@ -996,7 +996,7 @@ static void
>> emit_vlmax_masked_fp_mu_insn (unsigned icode, int op_num, rtx *ops)
>> {
>> machine_mode dest_mode = GET_MODE (ops[0]);
>> - machine_mode mask_mode = get_mask_mode (dest_mode).require ();
>> + machine_mode mask_mode = get_mask_mode (dest_mode);
>> insn_expander<RVV_INSN_OPERANDS_MAX> e (/*OP_NUM*/ op_num,
>> /*HAS_DEST_P*/ true,
>> /*FULLY_UNMASKED_P*/ false,
>> @@ -1054,7 +1054,7 @@ static void
>> emit_nonvlmax_tumu_insn (unsigned icode, int op_num, rtx *ops, rtx avl)
>> {
>> machine_mode dest_mode = GET_MODE (ops[0]);
>> - machine_mode mask_mode = get_mask_mode (dest_mode).require ();
>> + machine_mode mask_mode = get_mask_mode (dest_mode);
>> insn_expander<RVV_INSN_OPERANDS_MAX> e (/*OP_NUM*/ op_num,
>> /*HAS_DEST_P*/ true,
>> /*FULLY_UNMASKED_P*/ false,
>> @@ -1073,7 +1073,7 @@ static void
>> emit_nonvlmax_fp_tumu_insn (unsigned icode, int op_num, rtx *ops, rtx avl)
>> {
>> machine_mode dest_mode = GET_MODE (ops[0]);
>> - machine_mode mask_mode = get_mask_mode (dest_mode).require ();
>> + machine_mode mask_mode = get_mask_mode (dest_mode);
>> insn_expander<RVV_INSN_OPERANDS_MAX> e (/*OP_NUM*/ op_num,
>> /*HAS_DEST_P*/ true,
>> /*FULLY_UNMASKED_P*/ false,
>> @@ -1306,7 +1306,6 @@ void
>> expand_vec_series (rtx dest, rtx base, rtx step)
>> {
>> machine_mode mode = GET_MODE (dest);
>> - machine_mode mask_mode = get_mask_mode (mode);
>> poly_int64 nunits_m1 = GET_MODE_NUNITS (mode) - 1;
>> poly_int64 value;
>>
>> @@ -2375,7 +2374,6 @@ expand_vector_init_insert_elems (rtx target, const
>> rvv_builder &builder,
>> int nelts_reqd)
>> {
>> machine_mode mode = GET_MODE (target);
>> - machine_mode mask_mode = get_mask_mode (mode);
>> rtx dup = expand_vector_broadcast (mode, builder.elt (0));
>> emit_move_insn (target, dup);
>> int ndups = builder.count_dups (0, nelts_reqd - 1, 1);
>> --
>> 2.36.3
>>
