LGTM, I just found this patch still on the list, I mostly tested with
qemu, so I don't think that is a problem before, but I realize it's a
problem when we run on a real board that does not support those
extensions.
On Sun, Jun 18, 2023 at 6:07 AM Jeff Law via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
>
>
> On 6/15/23 09:06, Robin Dapp wrote:
> > Hi,
> >
> > Changes from v1:
> > - Revamped the target selectors again.
> > - Fixed some syntax as well as caching errors that were still present.
> > - Adjusted some test cases I missed.
> >
> > The current situation with target selectors is improvable at best.
> > We definitely need to discern between being able to build a
> > test with the current configuration and running the test on the
> > current target which this patch attempts to do. There might
> > be a need for more fine-grained checks in the future that could
> > also go into our target-specific riscv.exp in the subdirectories
> > but for now I think we're good.
> >
> > A bit more detail is in the patch description below. The testsuite
> > is as clean as before for the configurations I tried: default, rv64gcv,
> > rv64gcv_zfhmin, rv64gc, rv64gc_zfh, rv64gc_zfhmin. I hope I didn't
> > overlook tests that appear unsupported now but shouldn't be.
> >
> > @Pan: No need to check the old version anymore, thanks. This patch
> > is preferred.
> >
> > Regards
> > Robin
> >
> >
> > This introduces new checks for run tests. Currently we have
> > riscv_vector as well as rv32 and rv64 which all check if GCC (with the
> > current configuration) can build the respective tests.
> >
> > Many tests specify e.g. a different -march for vector which
> > makes the check fail even though we could build as well as run
> > those tests.
> >
> > vector_hw now tries to compile, link and execute a simple vector example
> > file. If this succeeds the respective test can run.
> >
> > Similarly we introduce a zvfh_hw check which will be used in the
> > upcoming floating-point unop/binop tests as well as rv32_hw and
> > rv64_hw checks that are currently unused.
> >
> > To conclude:
> > - If we want a testcase to only compile when the current configuration
> > has vector support we use {riscv_vector}.
> > - If we want a testcase to run when the current target can supports
> > executing vector instructions we use {riscv_vector_hw}.
> > It still needs to be ensured that we can actually build the test
> > which can be achieved by either
> > (1) compiling with e.g. -march=rv64gcv or
> > (2) only enabling the test when the current configuration supports
> > vector via {riscsv_vector}.
> >
> > The same principle applies for zfh, zfhmin and zvfh but we do not yet
> > have all target selectors. In the meanwhile we need to make sure to
> > specify the proper -march flags like in (1).
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/rvv/autovec/binop/shift-run.c: Use
> > riscv_vector_hw.
> > * gcc.target/riscv/rvv/autovec/binop/shift-scalar-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vadd-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vand-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vdiv-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vmax-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vmin-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vmul-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vor-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vrem-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vsub-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/binop/vxor-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-1.c: Dito.
> > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-2.c: Dito.
> > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-3.c: Dito.
> > * gcc.target/riscv/rvv/autovec/cmp/vcond_run-4.c: Dito.
> > * gcc.target/riscv/rvv/autovec/conversions/vfcvt_rtz-run.c:
> > Dito.
> > * gcc.target/riscv/rvv/autovec/conversions/vncvt-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/conversions/vsext-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/conversions/vzext-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-1.c:
> > Dito.
> > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c:
> > Dito.
> > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-3.c:
> > Dito.
> > * gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-4.c:
> > Dito.
> > * gcc.target/riscv/rvv/autovec/partial/single_rgroup_run-1.c:
> > Dito.
> > * gcc.target/riscv/rvv/autovec/partial/slp_run-1.c: Dito.
> > * gcc.target/riscv/rvv/autovec/partial/slp_run-2.c: Dito.
> > * gcc.target/riscv/rvv/autovec/partial/slp_run-3.c: Dito.
> > * gcc.target/riscv/rvv/autovec/partial/slp_run-4.c: Dito.
> > * gcc.target/riscv/rvv/autovec/partial/slp_run-5.c: Dito.
> > * gcc.target/riscv/rvv/autovec/partial/slp_run-6.c: Dito.
> > * gcc.target/riscv/rvv/autovec/partial/slp_run-7.c: Dito.
> > * gcc.target/riscv/rvv/autovec/series_run-1.c: Dito.
> > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-1.c: Dito.
> > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-2.c: Dito.
> > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-3.c: Dito.
> > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: Dito.
> > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: Dito.
> > * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: Dito.
> > * gcc.target/riscv/rvv/autovec/unop/abs-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/unop/vneg-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/unop/vnot-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-1.c:
> > Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-2.c:
> > Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/init-repeat-sequence-run-3.c:
> > Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-1.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/insert_run-2.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-1.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-2.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-3.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-4.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-5.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-6.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/perm_run-7.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-1.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-2.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-4.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-5.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-6.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vmv-imm-run.c: Dito.
> > * gcc.target/riscv/rvv/autovec/widen/widen_run-1.c: Dito.
> > * gcc.target/riscv/rvv/autovec/widen/widen_run-2.c: Dito.
> > * gcc.target/riscv/rvv/autovec/widen/widen_run-3.c: Dito.
> > * gcc.target/riscv/rvv/autovec/widen/widen_run-4.c: Dito.
> > * gcc.target/riscv/rvv/autovec/widen/widen_run-5.c: Dito.
> > * gcc.target/riscv/rvv/autovec/widen/widen_run-6.c: Dito.
> > * gcc.target/riscv/rvv/autovec/widen/widen_run-7.c: Dito.
> > * gcc.target/riscv/rvv/autovec/widen/widen_run-8.c: Dito.
> > * gcc.target/riscv/rvv/autovec/widen/widen_run-9.c: Dito.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-1.c: Use.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-2.c: Use.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-3.c: Use.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-4.c: Use.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-5.c: Use.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-6.c: Use.
> > * gcc.target/riscv/rvv/autovec/vls-vlmax/merge_run-7.c: Use.
> > * g++.target/riscv/rvv/base/bug-10.C: Use.
> > * g++.target/riscv/rvv/base/bug-11.C: Use.
> > * g++.target/riscv/rvv/base/bug-12.C: Use.
> > * g++.target/riscv/rvv/base/bug-13.C: Use.
> > * g++.target/riscv/rvv/base/bug-14.C: Use.
> > * g++.target/riscv/rvv/base/bug-15.C: Use.
> > * g++.target/riscv/rvv/base/bug-16.C: Use.
> > * g++.target/riscv/rvv/base/bug-17.C: Use.
> > * g++.target/riscv/rvv/base/bug-2.C: Use.
> > * g++.target/riscv/rvv/base/bug-23.C: Use.
> > * g++.target/riscv/rvv/base/bug-3.C: Use.
> > * g++.target/riscv/rvv/base/bug-4.C: Use.
> > * g++.target/riscv/rvv/base/bug-5.C: Use.
> > * g++.target/riscv/rvv/base/bug-6.C: Use.
> > * g++.target/riscv/rvv/base/bug-7.C: Use.
> > * g++.target/riscv/rvv/base/bug-8.C: Use.
> > * g++.target/riscv/rvv/base/bug-9.C: Use.
> > * lib/target-supports.exp: Add riscv_vect_hw, rv32_hw, rv64_hw
> > and zfh_hw, zfhmin_hw, zvfh_hw checks.
> I'm OK with the basic idea here and the dejagnu bits look reasonable.
> So I think the only question is whether or not others agree with the
> basic direction on the testsuite.
>
> So let's give the other RISC-V contributors a couple days to chime in.
>
> Jeff
