Address comments.
V3:
https://gcc.gnu.org/pipermail/gcc-patches/2023-July/625618.html
juzhe.zh...@rivai.ai
From: Kito Cheng
Date: 2023-07-27 14:52
To: Juzhe-Zhong
CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V2] RISC-V: Enable basic VLS modes support
Hi Juzhe-Zhong:
Only
> diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md
> new file mode 100644
> index 00000000000..c67ff386e50
> --- /dev/null
> +++ b/gcc/config/riscv/autovec-vls.md
> +(define_insn_and_split "mov<mode>"
> + [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> + (match_operand:VLS_AVL_IMM 1 "general_operand" " m,vr, vr"))]
> + "TARGET_VECTOR"
> + "@
> + #
> + #
> + vmv%m1r.v\t%0,%1"
> + "&& (!register_operand (operands[0], <MODE>mode)
> + || !register_operand (operands[1], <MODE>mode))"
> + [(const_int 0)]
> + {
> + unsigned size = GET_MODE_BITSIZE (<MODE>mode).to_constant ();
> + if (size <= MAX_BITS_PER_WORD
> + && MEM_P (operands[0]) && MEM_P (operands[1]))
I am thinking, is it possible to split this part into a standalone
define_split pattern
and be guarded with can_create_pseudo_p ()?
Since this should not work after RA, and also will cause some
suboptimal code for those modes larger than MAX_BITS_PER_WORD.
Consider that case: the mode size is larger than MAX_BITS_PER_WORD,
and the it get combined into (set (mem) (mem)), but RA didn't found
suitable constraint...so go to reload
And then we can add some check on this mov pattern to constrain it to
must be at least one
register operand like other mov patterns.
> +
> +(define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
> + [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
> + (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
> + (clobber (match_scratch:P 2 "=&r,&r,X"))]
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Add && (register_operand (operands[0], <MODE>mode) || register_operand
(operands[1], <MODE>mode))
