Re: [PATCH v2] RISC-V: optim const DF +0.0 store to mem [PR/110748]

[Jeff Law via Gcc-patches]

On 7/21/23 12:30, Vineet Gupta wrote:

Fixes: ef85d150b5963 ("RISC-V: Enable TARGET_SUPPORTS_WIDE_INT")
(gcc-13 regression)

DF +0.0 is bitwise all zeros so int x0 store to mem can be used to optimize it.

void zd(double *) { *d = 0.0; }

currently:

| fmv.d.x fa5,zero
| fsd     fa5,0(a0)
| ret

With patch

| sd      zero,0(a0)
| ret

This came to light when testing the in-flight f-m-o patch where an ICE
was getting triggered due to lack of this pattern but turns out this
is an independent optimization of its own [1]

[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-July/624857.html

Ran thru full multilib testsuite, there was 1 false failure due to
random string "lw" appearing in lto build assembler output, which is
also fixed in the patch.

gcc/Changelog:

        PR target/110748
        * config/riscv/predicates.md (const_0_operand): Add back
          const_double.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/pr110748-1.c: New Test.
        * gcc.target/riscv/xtheadfmv-fmv.c: Add '\t' around test
          patterns to avoid random string matches.

OK
jeff