On 7/19/23 16:45, Juzhe-Zhong wrote:
Current machine modes layout is hard to maintain && read && understand.
For a LMUL = 1 SI vector mode:
1. VNx1SI mode when TARGET_MIN_VLEN = 32.
2. VNx2SI mode when TARGET_MIN_VLEN = 64.
3. VNx4SI mode when TARGET_MIN_VLEN = 128.
Such implementation produces redundant machine modes and thus redudant machine
description patterns.
Now, this patch refactor machine modes into 3 follow formats:
1. mask mode: RVVMF64BImode, RVVMF32BImode, ...., RVVM1BImode.
RVVMF64BImode means such mask mode occupy 1/64 of a RVV M1 reg.
RVVM1BImode size = LMUL = 1 reg.
2. non-tuple vector modes:
RVV<LMUL><BASE_MODE>: E.g. RVVMF8QImode = SEW = 8 && LMUL = MF8
3. tuple vector modes:
RVV<LMUL>x<NF><BASE_MODE>.
For example, for SEW = 16, LMUL = MF2 , int mode is always RVVMF4HImode, then
adjust its size according to TARGET_MIN_VLEN.
Before this patch, the machine description patterns: 17551
After this patch, the machine description patterns: 14132 =====> reduce 3K+
patterns.
Regression of gcc/g++ rv32/rv64 all passed.
I haven't had a chance to look at this yet. But does it change
insn-emit.cc in any significant way? Particularly the maybe_code_for_*
functions which I think are playing a major role in the build time
regressions we're seeing, particularly native builds in qemu.
jeff
