From: Lulu Cheng <chengl...@loongson.cn>
gcc/ChangeLog:
* config/loongarch/genopts/loongarch-strings: Added compilation
framework.
* config/loongarch/genopts/loongarch.opt.in: Ditto.
* config/loongarch/loongarch-c.cc (loongarch_cpu_cpp_builtins): Ditto.
* config/loongarch/loongarch-def.c: Ditto.
* config/loongarch/loongarch-def.h (N_ISA_EXT_TYPES): Ditto.
(ISA_EXT_SIMD_LASX): Ditto.
(N_SWITCH_TYPES): Ditto.
(SW_LASX): Ditto.
* config/loongarch/loongarch-driver.cc (driver_get_normalized_m_opts):
Ditto.
* config/loongarch/loongarch-driver.h (driver_get_normalized_m_opts):
Ditto.
* config/loongarch/loongarch-opts.cc (isa_str): Ditto.
* config/loongarch/loongarch-opts.h (ISA_HAS_LSX): Ditto.
(ISA_HAS_LASX): Ditto.
* config/loongarch/loongarch-str.h (OPTSTR_LASX): Ditto.
* config/loongarch/loongarch.opt: Ditto.
---
gcc/config/loongarch/genopts/loongarch-strings | 1 +
gcc/config/loongarch/genopts/loongarch.opt.in | 4 ++++
gcc/config/loongarch/loongarch-c.cc | 11 +++++++++++
gcc/config/loongarch/loongarch-def.c | 4 +++-
gcc/config/loongarch/loongarch-def.h | 6 ++++--
gcc/config/loongarch/loongarch-driver.cc | 2 +-
gcc/config/loongarch/loongarch-driver.h | 1 +
gcc/config/loongarch/loongarch-opts.cc | 9 ++++++++-
gcc/config/loongarch/loongarch-opts.h | 4 +++-
gcc/config/loongarch/loongarch-str.h | 1 +
gcc/config/loongarch/loongarch.opt | 4 ++++
11 files changed, 41 insertions(+), 6 deletions(-)
diff --git a/gcc/config/loongarch/genopts/loongarch-strings
b/gcc/config/loongarch/genopts/loongarch-strings
index 24a5025061f..35d08f5967d 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -42,6 +42,7 @@ OPTSTR_DOUBLE_FLOAT double-float
# SIMD extensions
OPTSTR_LSX lsx
+OPTSTR_LASX lasx
# -mabi=
OPTSTR_ABI_BASE abi
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in
b/gcc/config/loongarch/genopts/loongarch.opt.in
index 338d77a7e40..afde23c9661 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -80,6 +80,10 @@ m@@OPTSTR_LSX@@
Target RejectNegative Var(la_opt_switches) Mask(LSX) Negative(m@@OPTSTR_LSX@@)
Enable LoongArch SIMD Extension (LSX).
+m@@OPTSTR_LASX@@
+Target RejectNegative Var(la_opt_switches) Mask(LASX)
Negative(m@@OPTSTR_LASX@@)
+Enable LoongArch Advanced SIMD Extension (LASX).
+
;; Base target models (implies ISA & tune parameters)
Enum
Name(cpu_type) Type(int)
diff --git a/gcc/config/loongarch/loongarch-c.cc
b/gcc/config/loongarch/loongarch-c.cc
index b065921adc3..2747fb9e472 100644
--- a/gcc/config/loongarch/loongarch-c.cc
+++ b/gcc/config/loongarch/loongarch-c.cc
@@ -104,8 +104,19 @@ loongarch_cpu_cpp_builtins (cpp_reader *pfile)
builtin_define ("__loongarch_simd");
builtin_define ("__loongarch_sx");
builtin_define ("__loongarch_sx_width=128");
+
+ if (!ISA_HAS_LASX)
+ builtin_define ("__loongarch_simd_width=128");
}
+ if (ISA_HAS_LASX)
+ {
+ builtin_define ("__loongarch_asx");
+ builtin_define ("__loongarch_asx_width=256");
+ builtin_define ("__loongarch_simd_width=256");
+ }
+
+
/* Native Data Sizes. */
builtin_define_with_int_value ("_LOONGARCH_SZINT", INT_TYPE_SIZE);
builtin_define_with_int_value ("_LOONGARCH_SZLONG", LONG_TYPE_SIZE);
diff --git a/gcc/config/loongarch/loongarch-def.c
b/gcc/config/loongarch/loongarch-def.c
index 28e24c62249..bff92c86532 100644
--- a/gcc/config/loongarch/loongarch-def.c
+++ b/gcc/config/loongarch/loongarch-def.c
@@ -54,7 +54,7 @@ loongarch_cpu_default_isa[N_ARCH_TYPES] = {
[CPU_LA464] = {
.base = ISA_BASE_LA64V100,
.fpu = ISA_EXT_FPU64,
- .simd = ISA_EXT_SIMD_LSX,
+ .simd = ISA_EXT_SIMD_LASX,
},
};
@@ -150,6 +150,7 @@ loongarch_isa_ext_strings[N_ISA_EXT_TYPES] = {
[ISA_EXT_FPU32] = STR_ISA_EXT_FPU32,
[ISA_EXT_NOFPU] = STR_ISA_EXT_NOFPU,
[ISA_EXT_SIMD_LSX] = OPTSTR_LSX,
+ [ISA_EXT_SIMD_LASX] = OPTSTR_LASX,
};
const char*
@@ -180,6 +181,7 @@ loongarch_switch_strings[] = {
[SW_SINGLE_FLOAT] = OPTSTR_SINGLE_FLOAT,
[SW_DOUBLE_FLOAT] = OPTSTR_DOUBLE_FLOAT,
[SW_LSX] = OPTSTR_LSX,
+ [SW_LASX] = OPTSTR_LASX,
};
diff --git a/gcc/config/loongarch/loongarch-def.h
b/gcc/config/loongarch/loongarch-def.h
index f34cffcfb9b..0bbcdb03d22 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -64,7 +64,8 @@ extern const char* loongarch_isa_ext_strings[];
#define ISA_EXT_FPU64 2
#define N_ISA_EXT_FPU_TYPES 3
#define ISA_EXT_SIMD_LSX 3
-#define N_ISA_EXT_TYPES 4
+#define ISA_EXT_SIMD_LASX 4
+#define N_ISA_EXT_TYPES 5
/* enum abi_base */
extern const char* loongarch_abi_base_strings[];
@@ -99,7 +100,8 @@ extern const char* loongarch_switch_strings[];
#define SW_SINGLE_FLOAT 1
#define SW_DOUBLE_FLOAT 2
#define SW_LSX 3
-#define N_SWITCH_TYPES 4
+#define SW_LASX 4
+#define N_SWITCH_TYPES 5
/* The common default value for variables whose assignments
are triggered by command-line options. */
diff --git a/gcc/config/loongarch/loongarch-driver.cc
b/gcc/config/loongarch/loongarch-driver.cc
index aa5011bd86a..3b9605de35f 100644
--- a/gcc/config/loongarch/loongarch-driver.cc
+++ b/gcc/config/loongarch/loongarch-driver.cc
@@ -181,7 +181,7 @@ driver_get_normalized_m_opts (int argc, const char **argv)
if (la_target.isa.simd)
{
- APPEND_LTR (" %<m" OPTSTR_LSX " -m");
+ APPEND_LTR (" %<m" OPTSTR_LSX " %<m" OPTSTR_LASX " -m");
APPEND_VAL (loongarch_isa_ext_strings[la_target.isa.simd]);
}
diff --git a/gcc/config/loongarch/loongarch-driver.h
b/gcc/config/loongarch/loongarch-driver.h
index db663818b7c..0c6b4157261 100644
--- a/gcc/config/loongarch/loongarch-driver.h
+++ b/gcc/config/loongarch/loongarch-driver.h
@@ -52,6 +52,7 @@ driver_get_normalized_m_opts (int argc, const char **argv);
LA_SET_FLAG_SPEC (SINGLE_FLOAT) \
LA_SET_FLAG_SPEC (DOUBLE_FLOAT) \
LA_SET_FLAG_SPEC (LSX) \
+ LA_SET_FLAG_SPEC (LASX) \
" %:get_normalized_m_opts()"
#define DRIVER_SELF_SPECS \
diff --git a/gcc/config/loongarch/loongarch-opts.cc
b/gcc/config/loongarch/loongarch-opts.cc
index 9753cf1290b..5986a2dd456 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -84,6 +84,7 @@ const int loongarch_switch_mask[N_SWITCH_TYPES] = {
/* SW_SINGLE_FLOAT */ M(FORCE_F32),
/* SW_DOUBLE_FLOAT */ M(FORCE_F64),
/* SW_LSX */ M(LSX),
+ /* SW_LASX */ M(LASX),
};
#undef M
@@ -254,8 +255,9 @@ config_target_isa:
t.isa.fpu : DEFAULT_ISA_EXT_FPU);
/* LoongArch SIMD extensions. */
+ /* Note: LASX implies LSX, so we put "on (LASX)" first. */
int simd_switch;
- if (on (LSX))
+ if (on (LASX) || on (LSX))
{
constrained.simd = 1;
switch (on_switch)
@@ -264,6 +266,10 @@ config_target_isa:
t.isa.simd = ISA_EXT_SIMD_LSX;
break;
+ case SW_LASX:
+ t.isa.simd = ISA_EXT_SIMD_LASX;
+ break;
+
default:
gcc_unreachable ();
}
@@ -603,6 +609,7 @@ isa_str (const struct loongarch_isa *isa, char separator)
switch (isa->simd)
{
case ISA_EXT_SIMD_LSX:
+ case ISA_EXT_SIMD_LASX:
APPEND1 (separator);
APPEND_STRING (loongarch_isa_ext_strings[isa->simd]);
break;
diff --git a/gcc/config/loongarch/loongarch-opts.h
b/gcc/config/loongarch/loongarch-opts.h
index d067c05dfc9..59a383ec5ca 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -66,7 +66,9 @@ loongarch_config_target (struct loongarch_target *target,
|| la_target.abi.base == ABI_BASE_LP64F \
|| la_target.abi.base == ABI_BASE_LP64S)
-#define ISA_HAS_LSX (la_target.isa.simd == ISA_EXT_SIMD_LSX)
+#define ISA_HAS_LSX (la_target.isa.simd == ISA_EXT_SIMD_LSX \
+ || la_target.isa.simd == ISA_EXT_SIMD_LASX)
+#define ISA_HAS_LASX (la_target.isa.simd == ISA_EXT_SIMD_LASX)
#define TARGET_ARCH_NATIVE (la_target.cpu_arch == CPU_NATIVE)
#define LARCH_ACTUAL_ARCH (TARGET_ARCH_NATIVE \
? (la_target.cpu_native < N_ARCH_TYPES \
diff --git a/gcc/config/loongarch/loongarch-str.h
b/gcc/config/loongarch/loongarch-str.h
index 6fa1b1571c5..951f35a3c24 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -43,6 +43,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTSTR_DOUBLE_FLOAT "double-float"
#define OPTSTR_LSX "lsx"
+#define OPTSTR_LASX "lasx"
#define OPTSTR_ABI_BASE "abi"
#define STR_ABI_BASE_LP64D "lp64d"
diff --git a/gcc/config/loongarch/loongarch.opt
b/gcc/config/loongarch/loongarch.opt
index 5c7e6d37220..611629b4203 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -87,6 +87,10 @@ mlsx
Target RejectNegative Var(la_opt_switches) Mask(LSX) Negative(mlsx)
Enable LoongArch SIMD Extension (LSX).
+mlasx
+Target RejectNegative Var(la_opt_switches) Mask(LASX) Negative(mlasx)
+Enable LoongArch Advanced SIMD Extension (LASX).
+
;; Base target models (implies ISA & tune parameters)
Enum
Name(cpu_type) Type(int)
--
2.36.0
