Hi, Richard.
RISC-V port needs to add a bunch VLS modes (V16QI,V32QI,V64QI,...etc)
There are sharing same REG_CLASS with VLA modes (VNx16QI,VNx32QI,...etc)
When I am adding those VLS modes, the RTL_SSA initialization in VSETVL PASS
(inserted after RA) ICE:
rvv.c:13:1: internal compiler error: in partial_subreg_p, at rtl.h:3186
13 | }
| ^
0xf7a5b1 partial_subreg_p(machine_mode, machine_mode)
../../../riscv-gcc/gcc/rtl.h:3186
0x1407616 wider_subreg_mode(machine_mode, machine_mode)
../../../riscv-gcc/gcc/rtl.h:3252
0x2a2c6ff rtl_ssa::combine_modes(machine_mode, machine_mode)
../../../riscv-gcc/gcc/rtl-ssa/internals.inl:677
0x2a2b9a4 rtl_ssa::function_info::simplify_phi_setup(rtl_ssa::phi_info*,
rtl_ssa::set_info**, bitmap_head*)
../../../riscv-gcc/gcc/rtl-ssa/functions.cc:146
0x2a2c142 rtl_ssa::function_info::simplify_phis()
../../../riscv-gcc/gcc/rtl-ssa/functions.cc:258
0x2a2b3f0 rtl_ssa::function_info::function_info(function*)
../../../riscv-gcc/gcc/rtl-ssa/functions.cc:51
0x1cebab9 pass_vsetvl::init()
../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4578
0x1cec150 pass_vsetvl::execute(function*)
../../../riscv-gcc/gcc/config/riscv/riscv-vsetvl.cc:4716
The reason is that we have V32QImode (size = [32,0]) which is the mode set as
regno_reg_rtx[97]
When the PHI input def comes from ENTRY BLOCK (index =0), the def->mode () =
V32QImode.
But the phi_mode = VNx2QI for example (I use VLA modes intrinsic write the
codes).
Then combine_modes report ICE.
In this situation, I relax it and let it use phi_mode directly.
Is it correct ?
Thanks.
gcc/ChangeLog:
* rtl-ssa/functions.cc (function_info::simplify_phi_setup): Relax
combine in PHI setup.
---
gcc/rtl-ssa/functions.cc | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/gcc/rtl-ssa/functions.cc b/gcc/rtl-ssa/functions.cc
index c35d25dbf8f..0793598ab1d 100644
--- a/gcc/rtl-ssa/functions.cc
+++ b/gcc/rtl-ssa/functions.cc
@@ -143,7 +143,19 @@ function_info::simplify_phi_setup (phi_info *phi, set_info
**assumed_values,
// If the input has a known mode (i.e. not BLKmode), make sure
// that the phi's mode is at least as large.
if (def)
- phi_mode = combine_modes (phi_mode, def->mode ());
+ {
+ /* For target like RISC-V, it applies both variable-length
+ and fixed-length to the same REG_CLASS.
+
+ It will cause ICE for these 2 following cases:
+ 1. phi_mode: variable-length.
+ def->mode (): fixed-length.
+ 2. phi_mode: fixed-length.
+ def->mode (): variable-length. */
+ if (!(GET_MODE_SIZE (phi_mode).is_constant ()
+ ^ GET_MODE_SIZE (def->mode ()).is_constant ()))
+ phi_mode = combine_modes (phi_mode, def->mode ());
+ }
}
if (phi->mode () != phi_mode)
phi->set_mode (phi_mode);
--
2.36.1
