Corresponding PR on c-api-doc under discussion, so defer this until that settles down :)
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/46 On Thu, Jul 13, 2023 at 1:40 PM Monk Chiang via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > gcc/ChangeLog: > > * config/riscv/riscv.cc (riscv_print_operand): > Add 'N' for print a non-temporal locality hints instruction. > * config/riscv/riscv.md (prefetch): > Add NTLH instruction for prefetch.r and prefetch.w. > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/prefetch-zihintntl.c: New test. > --- > gcc/config/riscv/riscv.cc | 22 +++++++++++++++++++ > gcc/config/riscv/riscv.md | 10 ++++++--- > .../gcc.target/riscv/prefetch-zihintntl.c | 20 +++++++++++++++++ > 3 files changed, 49 insertions(+), 3 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c > > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc > index 706c18416db..42f80088bab 100644 > --- a/gcc/config/riscv/riscv.cc > +++ b/gcc/config/riscv/riscv.cc > @@ -4532,6 +4532,7 @@ riscv_memmodel_needs_amo_release (enum memmodel model) > 'A' Print the atomic operation suffix for memory model OP. > 'I' Print the LR suffix for memory model OP. > 'J' Print the SC suffix for memory model OP. > + 'N' Print a non-temporal locality hints instruction. > 'z' Print x0 if OP is zero, otherwise print OP normally. > 'i' Print i if the operand is not a register. > 'S' Print shift-index of single-bit mask OP. > @@ -4718,6 +4719,27 @@ riscv_print_operand (FILE *file, rtx op, int letter) > break; > } > > + case 'N': > + { > + const char *ntl_hint = NULL; > + switch (INTVAL (op)) > + { > + case 0: > + ntl_hint = "ntl.all"; > + break; > + case 1: > + ntl_hint = "ntl.pall"; > + break; > + case 2: > + ntl_hint = "ntl.p1"; > + break; > + } > + > + if (ntl_hint) > + asm_fprintf (file, "%s\n\t", ntl_hint); > + break; > + } > + > case 'i': > if (code != REG) > fputs ("i", file); > diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md > index 7988026d129..3357c981b5d 100644 > --- a/gcc/config/riscv/riscv.md > +++ b/gcc/config/riscv/riscv.md > @@ -3256,11 +3256,15 @@ > { > switch (INTVAL (operands[1])) > { > - case 0: return "prefetch.r\t%a0"; > - case 1: return "prefetch.w\t%a0"; > + case 0: return TARGET_ZIHINTNTL ? "%N2prefetch.r\t%a0" : > "prefetch.r\t%a0"; > + case 1: return TARGET_ZIHINTNTL ? "%N2prefetch.w\t%a0" : > "prefetch.w\t%a0"; > default: gcc_unreachable (); > } > -}) > +} > + [(set (attr "length") (if_then_else (and (match_test "TARGET_ZIHINTNTL") > + (match_test "INTVAL (operands[2]) > != 3")) > + (const_string "8") > + (const_string "4")))]) > > (define_insn "riscv_prefetchi_<mode>" > [(unspec_volatile:X [(match_operand:X 0 "address_operand" "r") > diff --git a/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c > b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c > new file mode 100644 > index 00000000000..78a3afe6833 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/riscv/prefetch-zihintntl.c > @@ -0,0 +1,20 @@ > +/* { dg-do compile target { { rv64-*-*}}} */ > +/* { dg-options "-march=rv64gc_zicbop_zihintntl -mabi=lp64" } */ > + > +void foo (char *p) > +{ > + __builtin_prefetch (p, 0, 0); > + __builtin_prefetch (p, 0, 1); > + __builtin_prefetch (p, 0, 2); > + __builtin_prefetch (p, 0, 3); > + __builtin_prefetch (p, 1, 0); > + __builtin_prefetch (p, 1, 1); > + __builtin_prefetch (p, 1, 2); > + __builtin_prefetch (p, 1, 3); > +} > + > +/* { dg-final { scan-assembler-times "ntl.all" 2 } } */ > +/* { dg-final { scan-assembler-times "ntl.pall" 2 } } */ > +/* { dg-final { scan-assembler-times "ntl.p1" 2 } } */ > +/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ > +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ > -- > 2.40.1 >
