From: Christoph Müllner <christoph.muell...@vrull.eu>
Recently, two identical XTheadCondMov tests have been added, which both fail.
Let's fix that by changing the following:
* Merge both files into one (no need for separate tests for rv32 and rv64)
* Drop unrelated attribute check test (we already test for `th.mveqz`
and `th.mvnez` instructions, so there is little additional value)
* Fix the pattern to allow matching
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadcondmov-indirect-rv32.c: Moved to...
* gcc.target/riscv/xtheadcondmov-indirect.c: ...here.
* gcc.target/riscv/xtheadcondmov-indirect-rv64.c: Removed.
Fixes: a1806f0918c0 ("RISC-V: Optimize TARGET_XTHEADCONDMOV")
Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
---
.../riscv/xtheadcondmov-indirect-rv32.c | 104 ---------------
.../riscv/xtheadcondmov-indirect-rv64.c | 104 ---------------
.../gcc.target/riscv/xtheadcondmov-indirect.c | 118 ++++++++++++++++++
3 files changed, 118 insertions(+), 208 deletions(-)
delete mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
delete mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
deleted file mode 100644
index d0df59c5e1c..00000000000
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv32.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv32gc_xtheadcondmov -mabi=ilp32
-mriscv-attribute" } */
-/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Os" "-Og" "-O3" "-Oz" "-flto"} } */
-/* { dg-final { check-function-bodies "**" "" } } */
-
-/*
-**ConEmv_imm_imm_reg:
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
-** li\t\s*[a-x0-9]+,10+
-** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConEmv_imm_imm_reg(int x, int y){
- if (x == 1000) return 10;
- return y;
-}
-
-/*
-**ConEmv_imm_reg_reg:
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
-** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConEmv_imm_reg_reg(int x, int y, int z){
- if (x == 1000) return y;
- return z;
-}
-
-/*
-**ConEmv_reg_imm_reg:
-** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** li\t\s*[a-x0-9]+,10+
-** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConEmv_reg_imm_reg(int x, int y, int z){
- if (x == y) return 10;
- return z;
-}
-
-/*
-**ConEmv_reg_reg_reg:
-** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConEmv_reg_reg_reg(int x, int y, int z, int n){
- if (x == y) return z;
- return n;
-}
-
-/*
-**ConNmv_imm_imm_reg:
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
-** li\t\s*[a-x0-9]+,9998336+
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+
-** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConNmv_imm_imm_reg(int x, int y){
- if (x != 1000) return 10000000;
- return y;
-}
-
-/*
-**ConNmv_imm_reg_reg:
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
-** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConNmv_imm_reg_reg(int x, int y, int z){
- if (x != 1000) return y;
- return z;
-}
-
-/*
-**ConNmv_reg_imm_reg:
-** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** li\t\s*[a-x0-9]+,10+
-** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConNmv_reg_imm_reg(int x, int y, int z){
- if (x != y) return 10;
- return z;
-}
-
-/*
-**ConNmv_reg_reg_reg:
-** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConNmv_reg_reg_reg(int x, int y, int z, int n){
- if (x != y) return z;
- return n;
-}
-
-
-/* { dg-final { scan-assembler ".attribute arch,
\"rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadcondmov1p0\"" }
} */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
deleted file mode 100644
index cc971a75ace..00000000000
--- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect-rv64.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -march=rv64gc_xtheadcondmov -mabi=lp64d
-mriscv-attribute" } */
-/* { dg-skip-if "" { *-*-* } {"-O0" "-O1" "-Os" "-Og" "-O3" "-Oz" "-flto"} } */
-/* { dg-final { check-function-bodies "**" "" } } */
-
-/*
-**ConEmv_imm_imm_reg:
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
-** li\t\s*[a-x0-9]+,10+
-** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConEmv_imm_imm_reg(int x, int y){
- if (x == 1000) return 10;
- return y;
-}
-
-/*
-**ConEmv_imm_reg_reg:
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
-** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConEmv_imm_reg_reg(int x, int y, int z){
- if (x == 1000) return y;
- return z;
-}
-
-/*
-**ConEmv_reg_imm_reg:
-** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** li\t\s*[a-x0-9]+,10+
-** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConEmv_reg_imm_reg(int x, int y, int z){
- if (x == y) return 10;
- return z;
-}
-
-/*
-**ConEmv_reg_reg_reg:
-** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConEmv_reg_reg_reg(int x, int y, int z, int n){
- if (x == y) return z;
- return n;
-}
-
-/*
-**ConNmv_imm_imm_reg:
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
-** li\t\s*[a-x0-9]+,9998336+
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,1664+
-** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConNmv_imm_imm_reg(int x, int y){
- if (x != 1000) return 10000000;
- return y;
-}
-
-/*
-**ConNmv_imm_reg_reg:
-** addi\t\s*[a-x0-9]+,\s*[a-x0-9]+,-1000+
-** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConNmv_imm_reg_reg(int x, int y, int z){
- if (x != 1000) return y;
- return z;
-}
-
-/*
-**ConNmv_reg_imm_reg:
-** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** li\t\s*[a-x0-9]+,10+
-** th.mveqz\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConNmv_reg_imm_reg(int x, int y, int z){
- if (x != y) return 10;
- return z;
-}
-
-/*
-**ConNmv_reg_reg_reg:
-** sub\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** th.mvnez\t\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+
-** mv\t\s*[a-x0-9]+,\s*[a-x0-9]+
-** ret
-*/
-int ConNmv_reg_reg_reg(int x, int y, int z, int n){
- if (x != y) return z;
- return n;
-}
-
-
-/* { dg-final { scan-assembler ".attribute arch,
\"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_xtheadcondmov1p0\"" }
} */
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
new file mode 100644
index 00000000000..8292999d0c7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
@@ -0,0 +1,118 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+/*
+** ConEmv_imm_imm_reg:
+** addi a[0-9]+,a[0-9]+,-1000
+** li a[0-9]+,10
+** th\.mvnez a[0-9]+,a[0-9]+,a[0-9]+
+** ret
+*/
+int ConEmv_imm_imm_reg(int x, int y)
+{
+ if (x == 1000)
+ return 10;
+ return y;
+}
+
+/*
+** ConEmv_imm_reg_reg:
+** addi a[0-9]+,a[0-9]+,-1000
+** th.mveqz a[0-9]+,a[0-9]+,a[0-9]+
+** mv a[0-9]+,a[0-9]+
+** ret
+*/
+int ConEmv_imm_reg_reg(int x, int y, int z)
+{
+ if (x == 1000)
+ return y;
+ return z;
+}
+
+/*
+** ConEmv_reg_imm_reg:
+** sub a[0-9]+,a[0-9]+,a[0-9]+
+** li a[0-9]+,10
+** th.mvnez a[0-9]+,a[0-9]+,a[0-9]+
+** ret
+*/
+int ConEmv_reg_imm_reg(int x, int y, int z)
+{
+ if (x == y)
+ return 10;
+ return z;
+}
+
+/*
+** ConEmv_reg_reg_reg:
+** sub a[0-9]+,a[0-9]+,a[0-9]+
+** th.mveqz a[0-9]+,a[0-9]+,a[0-9]+
+** mv a[0-9]+,a[0-9]+
+** ret
+*/
+int ConEmv_reg_reg_reg(int x, int y, int z, int n)
+{
+ if (x == y)
+ return z;
+ return n;
+}
+
+/*
+** ConNmv_imm_imm_reg:
+** addi a[0-9]+,a[0-9]+,-1000+
+** li a[0-9]+,9998336+
+** addi a[0-9]+,a[0-9]+,1664+
+** th.mveqz a[0-9]+,a[0-9]+,a[0-9]+
+** ret
+*/
+int ConNmv_imm_imm_reg(int x, int y)
+{
+ if (x != 1000)
+ return 10000000;
+ return y;
+}
+
+/*
+**ConNmv_imm_reg_reg:
+** addi a[0-9]+,a[0-9]+,-1000+
+** th.mvnez a[0-9]+,a[0-9]+,a[0-9]+
+** mv a[0-9]+,a[0-9]+
+** ret
+*/
+int ConNmv_imm_reg_reg(int x, int y, int z)
+{
+ if (x != 1000)
+ return y;
+ return z;
+}
+
+/*
+**ConNmv_reg_imm_reg:
+** sub a[0-9]+,a[0-9]+,a[0-9]+
+** li a[0-9]+,10+
+** th.mveqz a[0-9]+,a[0-9]+,a[0-9]+
+** ret
+*/
+int ConNmv_reg_imm_reg(int x, int y, int z)
+{
+ if (x != y)
+ return 10;
+ return z;
+}
+
+/*
+**ConNmv_reg_reg_reg:
+** sub a[0-9]+,a[0-9]+,a[0-9]+
+** th.mvnez a[0-9]+,a[0-9]+,a[0-9]+
+** mv a[0-9]+,a[0-9]+
+** ret
+*/
+int ConNmv_reg_reg_reg(int x, int y, int z, int n)
+{
+ if (x != y)
+ return z;
+ return n;
+}
--
2.41.0
