> > +(define_insn "aarch64_<su>abdl<mode>_hi_internal" > > + [(set (match_operand:<VWIDE> 0 "register_operand" "=w") > > + (minus:<VWIDE> > > + (USMAX:<VWIDE> > > + (<USMAX_EXT>:<VWIDE> > > + (vec_select:<VHALF> > > + (match_operand:VQW 1 "register_operand" "w") > > + (match_operand:VQW 3 "vect_par_cnst_hi_half" ""))) > > + (<USMAX_EXT>:<VWIDE> > > + (vec_select:<VHALF> > > + (match_operand:VQW 2 "register_operand" "w") > > + (match_dup 3)))) > > + (<max_opp>:<VWIDE> > > + (<USMAX_EXT>:<VWIDE> > > + (vec_select:<VHALF> (match_dup 1) (match_dup 3))) > > + (<USMAX_EXT>:<VWIDE> > > + (vec_select:<VHALF> (match_dup 2) (match_dup 3))))))] > > + "TARGET_SIMD" > > + "<su>abdl2\t%0.<Vwtype>, %1.<Vtype>, %2.<Vtype>" > > + [(set_attr "type" "neon_abd_long")] > > +) > > We don't need the (minus (max…) (min…)) thing when widening is > involved. It should be enough to do something like: > > (abs:<VWIDE> > (minus:<VWIDE> > (ANY_EXTEND:<VWIDE> > (vec_select:…)) > (ANY_EXTEND:<VWIDE> > (vec_select:…))))
Change made. > Sorry to be awkward, but could you put the widening cases in a separate > file? It's not very easy as things stand to work out which tests are > matched against widening ops and which aren't. Done. Patch in next email.
