I was wondering whether I could ask a LRA/reload expert for their help with
a better fix with this issue.
For the testcase (from sse2-v1ti-mov-1.c):
typedef unsigned __int128 uv1ti __attribute__ ((__vector_size__ (16)));
uv1ti foo(__int128 x) { return (uv1ti)x; }
we currently generate (with -O2) the suboptimal:
movq %rdi, %xmm1
movq %rsi, %xmm2
punpcklqdq %xmm2, %xmm1
movdqa %xmm1, %xmm0
Notice that (due to register allocation) the result is calculated in
%xmm1 and in the final structure copied to the result %xmm0.
With the one line change (workaround) below, we generate the better
(optimal) sequence:
movq %rdi, %xmm0
movq %rsi, %xmm1
punpcklqdq %xmm1, %xmm0
The triggering event responsible for the current behaviour is that
combine merges the two instructions:
(insn 12 7 13 2 (set (reg:V2DI 88)
(vec_concat:V2DI (reg:DI 95)
(reg:DI 96))) "sse2-v1ti-mov-1.c":8:10 discrim 1 7238
{vec_concatv2di}
(expr_list:REG_DEAD (reg:DI 96)
(expr_list:REG_DEAD (reg:DI 95)
(nil))))
(insn 13 12 17 2 (set (reg:V1TI 82 [ <retval> ])
(subreg:V1TI (reg:V2DI 88) 0)) "sse2-v1ti-mov-1.c":8:10 discrim 1
1860 {movv1ti_internal}
(expr_list:REG_DEAD (reg:V2DI 88)
(nil)))
into the single instruction (with a SUBREG in the SET_DEST):
(insn 13 12 17 2 (set (subreg:V2DI (reg:V1TI 82 [ <retval> ]) 0)
(vec_concat:V2DI (reg:DI 95)
(reg:DI 96))) "sse2-v1ti-mov-1.c":8:10 discrim 1 7244
{vec_concatv2di}
(expr_list:REG_DEAD (reg:DI 95)
(expr_list:REG_DEAD (reg:DI 96)
(nil))))
Unfortunately, this form is challenging for lra/reload...
Choosing alt 4 in insn 13: (0) x (1) 0 (2) x {vec_concatv2di}
Creating newreg=98, assigning class SSE_REGS to r98
Creating newreg=99 from oldreg=96, assigning class SSE_REGS to r99
13: r98:V2DI=vec_concat(r98:V2DI#0,r99:DI)
REG_DEAD r96:DI
REG_DEAD r95:DI
Inserting insn reload before:
27: clobber r98:V2DI
28: r98:V2DI#0=r95:DI
30: r99:DI=r96:DI
Inserting insn reload after:
29: r82:V1TI#0=r98:V2DI
It's the clobber of r98 (insn 27) that's generated by the emit_clobber
at around line 1081 in match_reload from lra-constraints.cc that's critical,
causing r82 and r98 to occupy different registers/allocations. Is there
a way of preventing this clobber/conflict? Are V2DI and V1TI correctly
annotated as tieable to the same hard register.
This patch works by explicitly checking that the destination in
vec_concatv2di is a REG_P, i.e. not a SUBREG, and therefore preventing
the two instructions to be merged by combine. But clearly this is a
case where lra/reload could be doing better.
Thoughts?
2023-06-18 Roger Sayle <ro...@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/sse.md (vec_concatv2di): Require that the destination
is a REG_P (i.e. a pseudo or hard register, not a SUBREG).
Roger
--
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 70d7410..20a26a0 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -20060,7 +20060,7 @@
" 0, 0,x ,Yv,0,Yv,0,0,v")
(match_operand:DI 2 "nonimmediate_operand"
" rm,rm,rm,rm,x,Yv,x,m,m")))]
- "TARGET_SSE"
+ "TARGET_SSE && REG_P (operands[0])"
"@
pinsrq\t{$1, %2, %0|%0, %2, 1}
pinsrq\t{$1, %2, %0|%0, %2, 1}
