From: Pan Li <pan2...@intel.com>
This patch would like to add new test cases to make sure the
RVV FP16 works well as expected.
Signed-off-by: Pan Li <pan2...@intel.com>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Add new cases.
* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: New test.
---
.../riscv/rvv/base/zvfh-intrinsic.c | 22 ++++++++++-
.../riscv/rvv/base/zvfh-over-zvfhmin.c | 37 +++++++++++++++++++
2 files changed, 57 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index 2e86d1faaf1..c951644de4b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -413,9 +413,25 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1(vfloat16m8_t
vector, vfloat32m1_t sc
return __riscv_vfwredusum_vs_f16m8_f32m1(vector, scalar, vl);
}
-/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 49 } } */
+vfloat16mf4_t test_vfslide1up_vf_f16mf4(vfloat16mf4_t src, float16_t value,
size_t vl) {
+ return __riscv_vfslide1up_vf_f16mf4(src, value, vl);
+}
+
+vfloat16m8_t test_vfslide1up_vf_f16m8(vfloat16m8_t src, float16_t value,
size_t vl) {
+ return __riscv_vfslide1up_vf_f16m8(src, value, vl);
+}
+
+vfloat16mf4_t test_vfslide1down_vf_f16mf4(vfloat16mf4_t src, float16_t value,
size_t vl) {
+ return __riscv_vfslide1down_vf_f16mf4(src, value, vl);
+}
+
+vfloat16m8_t test_vfslide1down_vf_f16m8(vfloat16m8_t src, float16_t value,
size_t vl) {
+ return __riscv_vfslide1down_vf_f16m8(src, value, vl);
+}
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 51 } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 11 } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 40 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 42 } } */
/* { dg-final { scan-assembler-times
{vfadd\.v[fv]\s+v[0-9]+,\s*v[0-9]+,\s*[vfa]+[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times
{vfsub\.v[fv]\s+v[0-9]+,\s*v[0-9]+,\s*[vfa]+[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times
{vfrsub\.vf\s+v[0-9]+,\s*v[0-9]+,\s*[vfa]+[0-9]+} 2 } } */
@@ -470,3 +486,5 @@ vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1(vfloat16m8_t
vector, vfloat32m1_t sc
/* { dg-final { scan-assembler-times
{vfredmin\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times
{vfwredosum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
/* { dg-final { scan-assembler-times
{vfwredusum\.vs\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times
{vfslide1up\.vf\s+v[0-9]+,\s*v[0-9]+,\s*fa[0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times
{vfslide1down\.vf\s+v[0-9]+,\s*v[0-9]+,\s*fa[0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
new file mode 100644
index 00000000000..2afc105e2da
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
+
+#include "riscv_vector.h"
+
+typedef _Float16 float16_t;
+
+vfloat16mf4_t test_vfncvt_f_f_w_f16mf4(vfloat32mf2_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16mf4(src, vl);
+}
+
+vfloat16m4_t test_vfncvt_f_f_w_f16m4(vfloat32m8_t src, size_t vl) {
+ return __riscv_vfncvt_f_f_w_f16m4(src, vl);
+}
+
+vfloat32mf2_t test_vfwcvt_f_f_v_f32mf2(vfloat16mf4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32mf2(src, vl);
+}
+
+vfloat32m8_t test_vfwcvt_f_f_v_f32m8(vfloat16m4_t src, size_t vl) {
+ return __riscv_vfwcvt_f_f_v_f32m8(src, vl);
+}
+
+vfloat16mf4_t test_vle16_v_f16mf4(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16mf4(base, vl);
+}
+
+vfloat16m8_t test_vle16_v_f16m8(const float16_t *base, size_t vl) {
+ return __riscv_vle16_v_f16m8(base, vl);
+}
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2
} } */
+/* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2
} } */
+/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 3 }
} */
--
2.34.1
