Thanks Kito, update the PATCH v2 for addressing comments. https://gcc.gnu.org/pipermail/gcc-patches/2023-May/619868.html
Pan -----Original Message----- From: Kito Cheng <kito.ch...@gmail.com> Sent: Monday, May 29, 2023 10:18 AM To: Li, Pan2 <pan2...@intel.com> Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Wang, Yanzhang <yanzhang.w...@intel.com> Subject: Re: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option On Mon, May 29, 2023 at 9:32 AM Li, Pan2 via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > Sorry for disturbing but please help to take this PATCH in front of the > reviewing queue as it blocks the RVV FP16 intrinsic support. Thanks a lot. > > Pan > > -----Original Message----- > From: Li, Pan2 <pan2...@intel.com> > Sent: Thursday, May 25, 2023 8:46 PM > To: gcc-patches@gcc.gnu.org > Cc: juzhe.zh...@rivai.ai; kito.ch...@sifive.com; Li, Pan2 > <pan2...@intel.com>; Wang, Yanzhang <yanzhang.w...@intel.com> > Subject: [PATCH] RISC-V: Add ZVFHMIN extension to the -march= option > > From: Pan Li <pan2...@intel.com> > > This patch would like to add new sub extension (aka ZVFHMIN) to the -march= > option. To make it simple, only the sub extension itself is involved in this > patch, and the underlying FP16 related RVV intrinsic API depends on the > TARGET_ZVFHMIN. > > You can locate more information about ZVFHMIN from below spec doc. > > https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#zvfhmin- > vector-extension-for-minimal-half-precision-floating-point > > Signed-off-by: Pan Li <pan2...@intel.com> > > gcc/ChangeLog: > > * common/config/riscv/riscv-common.cc: > (riscv_implied_info): Add zvfhmin item. > (riscv_ext_version_table): Ditto. > (riscv_ext_flag_table): Ditto. > * config/riscv/riscv-opts.h (MASK_ZVFHMIN): New macro. > (TARGET_ZFHMIN): Align indent. > (TARGET_ZFH): Ditto. > (TARGET_ZVFHMIN): New macro. > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/arch-20.c: New test. > * gcc.target/riscv/predef-26.c: New test. > --- > gcc/common/config/riscv/riscv-common.cc | 3 ++ > gcc/config/riscv/riscv-opts.h | 6 ++- > gcc/testsuite/gcc.target/riscv/arch-20.c | 5 +++ > gcc/testsuite/gcc.target/riscv/predef-26.c | 51 > ++++++++++++++++++++++ > 4 files changed, 63 insertions(+), 2 deletions(-) create mode 100644 > gcc/testsuite/gcc.target/riscv/arch-20.c > create mode 100644 gcc/testsuite/gcc.target/riscv/predef-26.c > > diff --git a/gcc/common/config/riscv/riscv-common.cc > b/gcc/common/config/riscv/riscv-common.cc > index c2ec74b9d92..72f2f8f2753 100644 > --- a/gcc/common/config/riscv/riscv-common.cc > +++ b/gcc/common/config/riscv/riscv-common.cc > @@ -104,6 +104,7 @@ static const riscv_implied_info_t > riscv_implied_info[] = > > {"zfh", "zfhmin"}, > {"zfhmin", "f"}, > + {"zvfhmin", "f"}, spec says: "The Zvfhmin extension depends on the Zve32f extension." so this should be zve32f rather than f > {"zhinx", "zhinxmin"}, > {"zhinxmin", "zfinx"},
