LGTM
<juzhe.zh...@rivai.ai> 於 2023年5月26日 週五 08:46 寫道：
> From: Juzhe-Zhong <juzhe.zh...@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (vector_zero_call_used_regs): Add explict
> VL and drop VL in ops.
>
> ---
> gcc/config/riscv/riscv.cc | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 09fc9e5d95e..b16c60df6a7 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7396,9 +7396,9 @@ vector_zero_call_used_regs (HARD_REG_SET
> need_zeroed_hardregs)
> emitted_vlmax_vsetvl = true;
> }
>
> - rtx ops[] = {target, CONST0_RTX (mode), vl};
> + rtx ops[] = {target, CONST0_RTX (mode)};
> riscv_vector::emit_vlmax_insn (code_for_pred_mov (mode),
> - riscv_vector::RVV_UNOP, ops);
> + riscv_vector::RVV_UNOP, ops, vl);
>
> SET_HARD_REG_BIT (zeroed_hardregs, regno);
> }
> --
> 2.36.3
>
>
