On 5/25/23 07:50, Richard Biener wrote:
On Thu, May 25, 2023 at 3:32 PM Jeff Law via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
On 5/25/23 07:01, Richard Biener via Gcc-patches wrote:
On Thu, May 25, 2023 at 2:36 PM Manolis Tsamis <manolis.tsa...@vrull.eu> wrote:
Implementation of the new RISC-V optimization pass for memory offset
calculations, documentation and testcases.
Why do fwprop or combine not what you want to do?
I think a lot of them end up coming from register elimination.
Why isn't this a problem for other targets then? Or maybe it is and this
shouldn't be a machine specific pass? Maybe postreload-gcse should
perform strength reduction (I can't think of any other post reload pass
that would do something even remotely related).
It is to some degree. I ran into similar problems at my prior employer.
We ended up working around it in the target files in a different way
-- which didn't work when I quickly tried it on RISC-V.
Seems like it would be worth another investigative step as part of the
evaluation of this patch. I wasn't at 100% when I did that poking
around many months ago.
Jeff
