Hi Alexandre,
on 2023/5/24 13:51, Alexandre Oliva wrote:
>
> Codegen changes caused add instruction count mismatches on
> ppc-*-linux-gnu and other 32-bit ppc targets. At some point the
> expected counts were adjusted for lp64, but ilp32 differences
> remained, and published test results confirm it.
Thanks for fixing, I tested this on ppc64le and ppc64 {-m64,-m32}
well.
>
> Bootstrapped on x86_64-linux-gnu. Also tested on ppc- and x86-vx7r2
> with gcc-12.
>
> for gcc/testsuite/ChangeLog
I think this is for PR101169, could you add it as PR marker?
>
> * gcc.target/powerpc/fold-vec-extract-char.p7.c: Adjust addi
> counts for ilp32.
> * gcc.target/powerpc/fold-vec-extract-double.p7.c: Likewise.
> * gcc.target/powerpc/fold-vec-extract-float.p7.c: Likewise.
> * gcc.target/powerpc/fold-vec-extract-float.p8.c: Likewise.
> * gcc.target/powerpc/fold-vec-extract-int.p7.c: Likewise.
> * gcc.target/powerpc/fold-vec-extract-int.p8.c: Likewise.
> * gcc.target/powerpc/fold-vec-extract-short.p7.c: Likewise.
> * gcc.target/powerpc/fold-vec-extract-short.p8.c: Likewise.
> ---
> .../gcc.target/powerpc/fold-vec-extract-char.p7.c | 3 ++-
> .../powerpc/fold-vec-extract-double.p7.c | 2 +-
> .../gcc.target/powerpc/fold-vec-extract-float.p7.c | 2 +-
> .../gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
> .../gcc.target/powerpc/fold-vec-extract-int.p7.c | 2 +-
> .../gcc.target/powerpc/fold-vec-extract-int.p8.c | 2 +-
> .../gcc.target/powerpc/fold-vec-extract-short.p7.c | 2 +-
> .../gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
> 8 files changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
> index 29a8aa84db282..c6647431d09c9 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-char.p7.c
> @@ -11,7 +11,8 @@
> /* one extsb (extend sign-bit) instruction generated for each test against
> unsigned types */
>
> -/* { dg-final { scan-assembler-times {\maddi\M} 9 } } */
> +/* { dg-final { scan-assembler-times {\maddi\M} 9 { target { lp64 } } } } */
> +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target { ilp32 } } } } */
> /* { dg-final { scan-assembler-times {\mli\M} 6 } } */
> /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
> /* -m32 target uses rlwinm in place of rldicl. */
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
> index 3cae644b90b71..db325efbb07ff 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-double.p7.c
> @@ -14,7 +14,7 @@
> /* { dg-final { scan-assembler-times {\mli\M} 1 } } */
> /* -m32 target has an 'add' in place of one of the 'addi'. */
> /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } }
> } */
> -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } }
> } */
> +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target ilp32 } }
> } */
So both lp64 and ilp32 have the same count, could we merge it and remove the
selectors?
> /* -m32 target has a rlwinm in place of a rldic . */
> /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
> /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
> index 59a4979457dcb..42ec69475fd07 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p7.c
> @@ -13,7 +13,7 @@
> /* { dg-final { scan-assembler-times {\mli\M} 1 } } */
> /* -m32 as an add in place of an addi. */
> /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target lp64 } }
> } */
> -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 3 { target ilp32 } }
> } */
> +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 2 { target ilp32 } }
> } */
Ditto.
> /* { dg-final { scan-assembler-times {\mstxvd2x\M|\mstvx\M|\mstxv\M} 1 } } */
> /* -m32 uses rlwinm in place of rldic */
> /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 1 } } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
> index 4b1d75ee26d0f..68eeeede4b307 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-float.p8.c
> @@ -26,7 +26,7 @@
> /* { dg-final { scan-assembler-times {\mstxvd2x\M} 1 { target ilp32 } } } */
> /* { dg-final { scan-assembler-times {\madd\M} 1 { target ilp32 } } } */
> /* { dg-final { scan-assembler-times {\mlfs\M} 1 { target ilp32 } } } */
> -/* { dg-final { scan-assembler-times {\maddi\M} 2 { target ilp32 } } } */
> +/* { dg-final { scan-assembler-times {\maddi\M} 1 { target ilp32 } } } */
>
>
> #include <altivec.h>
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
> index 3729a1646e9c9..e8130693ee953 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p7.c
> @@ -11,7 +11,7 @@
>
> /* { dg-final { scan-assembler-times {\mli\M} 6 } } */
> /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } }
> } */
> -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 }
> } } */
> +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target ilp32 } }
> } */
Ditto.
> /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M|\mstxv\M} 6 } } */
> /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
> /* { dg-final { scan-assembler-times {\mlwz\M|\mlwa\M|\mlwzx\M|\mlwax\M} 6 }
> } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
> index 75eaf25943b70..d1e3b62373f80 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-int.p8.c
> @@ -30,7 +30,7 @@
> /* { dg-final { scan-assembler-times {\mstxvw4x\M} 6 { target ilp32 } } } */
> /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
> /* { dg-final { scan-assembler-times {\mlwz\M} 6 { target ilp32 } } } */
> -/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
> +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
>
>
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
> index a495d9f3928fa..ec3b78bac5df6 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p7.c
> @@ -11,7 +11,7 @@
>
> /* { dg-final { scan-assembler-times {\mli\M} 6 } } */
> /* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target lp64 } }
> } */
> -/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 12 { target ilp32 }
> } } */
> +/* { dg-final { scan-assembler-times {\maddi\M|\madd\M} 9 { target ilp32 } }
> } */
Ditto.
BR,
Kewen
> /* { dg-final { scan-assembler-times {\mrldic\M|\mrlwinm\M} 3 } } */
> /* { dg-final { scan-assembler-times {\mstxvw4x\M|\mstvx\M} 6 } } */
> /* { dg-final { scan-assembler-times "lhz|lha|lhzx|lhax" 6 } } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
> b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
> index 0ddecb4e4b55d..00685aca1367b 100644
> --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
> +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-extract-short.p8.c
> @@ -32,7 +32,7 @@
> /* add and rlwinm instructions only on the variable tests. */
> /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
> /* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */
> -/* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
> +/* { dg-final { scan-assembler-times {\maddi\M} 6 { target ilp32 } } } */
> /* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } }
> } */
>
>
>
