"juzhe.zh...@rivai.ai" <juzhe.zh...@rivai.ai> writes:
> Yeah. I know.
> Like ARM does everywhere:
> (define_expand "vcond<SVE_ALL:mode><SVE_I:mode>"
> [(set (match_operand:SVE_ALL 0 "register_operand")
> (if_then_else:SVE_ALL
> (match_operator 3 "comparison_operator"
> [(match_operand:SVE_I 4 "register_operand")
> (match_operand:SVE_I 5 "nonmemory_operand")])
> (match_operand:SVE_ALL 1 "nonmemory_operand")
> (match_operand:SVE_ALL 2 "nonmemory_operand")))]
> "TARGET_SVE && <SVE_ALL:container_bits> == <SVE_I:container_bits>"
> {
> aarch64_expand_sve_vcond (<SVE_ALL:MODE>mode, <SVE_I:MODE>mode, operands);
> DONE;
> }
> )
>
> passing "operands" looks codes much cleaner.
FWIW, I think we only do that when we're reusing optab patterns.
The handling of operand 3 is forced by the definition of vcond_optab.
When there's a choice, we generally use "@" patterns instead, and
pass codes and modes to the expander.
Thanks,
Richard
