ok, and also ok for those small API test in testsuite.
On Tue, May 16, 2023 at 9:10 AM Li, Pan2 via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Kindly ping for this PATCH, 😉.
>
> Pan
>
> From: Li, Pan2
> Sent: Monday, May 15, 2023 11:25 AM
> To: juzhe.zh...@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>
> Cc: Kito.cheng <kito.ch...@sifive.com>; Wang, Yanzhang
> <yanzhang.w...@intel.com>
> Subject: RE: [PATCH] RISC-V: Support RVV VREINTERPRET from v{u}int*_t to
> vbool1_t
>
> Thanks Juzhe. Let’s wait kito’s suggestion.
>
> Pan
>
> From: juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
> <juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>>
> Sent: Monday, May 15, 2023 11:20 AM
> To: Li, Pan2 <pan2...@intel.com<mailto:pan2...@intel.com>>; gcc-patches
> <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
> Cc: Kito.cheng <kito.ch...@sifive.com<mailto:kito.ch...@sifive.com>>; Li,
> Pan2 <pan2...@intel.com<mailto:pan2...@intel.com>>; Wang, Yanzhang
> <yanzhang.w...@intel.com<mailto:yanzhang.w...@intel.com>>
> Subject: Re: [PATCH] RISC-V: Support RVV VREINTERPRET from v{u}int*_t to
> vbool1_t
>
> The implementation LGTM.
> But I am not sure testcase since we don't include any intrinsic API testcases
> in GCC testsuite.
> I think it needs Kito's decision.
>
> Thanks.
> ________________________________
> juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai>
>
> From: pan2.li<mailto:pan2...@intel.com>
> Date: 2023-05-15 11:14
> To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>;
> kito.cheng<mailto:kito.ch...@sifive.com>; pan2.li<mailto:pan2...@intel.com>;
> yanzhang.wang<mailto:yanzhang.w...@intel.com>
> Subject: [PATCH] RISC-V: Support RVV VREINTERPRET from v{u}int*_t to vbool1_t
> From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>>
>
> This patch support the RVV VREINTERPRET from the int to the vbool1_t. Aka:
>
> vbool1_t __riscv_vreinterpret_xx_xx(v{u}int[8|16|32|64]_t);
>
> These APIs help the users to convert vector LMUL=1 integer to vbool1_t.
> According to the RVV intrinsic SPEC as below, the reinterpret intrinsics
> only change the types of the underlying contents.
>
> https://github.com/riscv-non-isa/rvv-intrinsic-doc/blob/master/rvv-intrinsic-rfc.md#reinterpret-vbool-o-vintm1
>
> For example, given below code.
> vbool1_t test_vreinterpret_v_i8m1_b1(vint8m1_t src) {
> return __riscv_vreinterpret_v_i8m1_b1(src);
> }
>
> It will generate the assembly code similar as below:
> vsetvli a5,zero,e8,m8,ta,ma
> vlm.v v1,0(a1)
> vsm.v v1,0(a0)
> ret
>
> The rest intrinsic bool size APIs will be prepared in other PATCH.
>
> Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>>
>
> gcc/ChangeLog:
>
> * config/riscv/genrvv-type-indexer.cc (BOOL_SIZE_LIST): New
> macro.
> (main): Add bool1 to the type indexer.
> * config/riscv/riscv-vector-builtins-functions.def
> (vreinterpret): Register vbool1 interpret function.
> * config/riscv/riscv-vector-builtins-types.def
> (DEF_RVV_BOOL1_INTERPRET_OPS): New macro.
> (vint8m1_t): Add the type to bool1_interpret_ops.
> (vint16m1_t): Ditto.
> (vint32m1_t): Ditto.
> (vint64m1_t): Ditto.
> (vuint8m1_t): Ditto.
> (vuint16m1_t): Ditto.
> (vuint32m1_t): Ditto.
> (vuint64m1_t): Ditto.
> * config/riscv/riscv-vector-builtins.cc
> (DEF_RVV_BOOL1_INTERPRET_OPS): New macro.
> (required_extensions_p): Add bool1 interpret case.
> * config/riscv/riscv-vector-builtins.def
> (bool1_interpret): Add bool1 interpret to base type.
> * config/riscv/vector.md (@vreinterpret<mode>): Add new expand
> with VB dest for vreinterpret.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: New test.
> ---
> gcc/config/riscv/genrvv-type-indexer.cc | 19 ++++++++++
> .../riscv/riscv-vector-builtins-functions.def | 1 +
> .../riscv/riscv-vector-builtins-types.def | 17 +++++++++
> gcc/config/riscv/riscv-vector-builtins.cc | 18 +++++++++
> gcc/config/riscv/riscv-vector-builtins.def | 2 +
> gcc/config/riscv/vector.md | 10 +++++
> .../rvv/base/misc_vreinterpret_vbool_vint.c | 38 +++++++++++++++++++
> 7 files changed, 105 insertions(+)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
>
> diff --git a/gcc/config/riscv/genrvv-type-indexer.cc
> b/gcc/config/riscv/genrvv-type-indexer.cc
> index 9bf6a82601d..2f0375568a8 100644
> --- a/gcc/config/riscv/genrvv-type-indexer.cc
> +++ b/gcc/config/riscv/genrvv-type-indexer.cc
> @@ -23,6 +23,8 @@ along with GCC; see the file COPYING3. If not see
> #include <assert.h>
> #include <math.h>
> +#define BOOL_SIZE_LIST {1}
> +
> std::string
> to_lmul (int lmul_log2)
> {
> @@ -218,6 +220,9 @@ main (int argc, const char **argv)
> for (unsigned eew : {8, 16, 32, 64})
> fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew);
> + for (unsigned boolsize : BOOL_SIZE_LIST)
> + fprintf (fp, " /*BOOL%d_INTERPRET*/ INVALID,\n", boolsize);
> +
> for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
> {
> unsigned multiple_of_lmul = 1 << lmul_log2_offset;
> @@ -297,6 +302,16 @@ main (int argc, const char **argv)
> inttype (eew, lmul_log2, unsigned_p).c_str ());
> }
> + for (unsigned boolsize : BOOL_SIZE_LIST)
> + {
> + std::stringstream mode;
> + mode << "vbool" << boolsize << "_t";
> +
> + fprintf (fp, " /*BOOL%d_INTERPRET*/ %s,\n", boolsize,
> + nf == 1 && lmul_log2 == 0 ? mode.str ().c_str ()
> + : "INVALID");
> + }
> +
> for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
> {
> unsigned multiple_of_lmul = 1 << lmul_log2_offset;
> @@ -355,6 +370,10 @@ main (int argc, const char **argv)
> floattype (sew * 2, /*lmul_log2*/ 0).c_str ());
> for (unsigned eew : {8, 16, 32, 64})
> fprintf (fp, " /*EEW%d_INTERPRET*/ INVALID,\n", eew);
> +
> + for (unsigned boolsize : BOOL_SIZE_LIST)
> + fprintf (fp, " /*BOOL%d_INTERPRET*/ INVALID,\n", boolsize);
> +
> for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
> {
> unsigned multiple_of_lmul = 1 << lmul_log2_offset;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 7200036d853..72032c6a52c 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -508,6 +508,7 @@ DEF_RVV_FUNCTION (vreinterpret, misc, none_preds,
> iu_v_eew8_interpret_ops)
> DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew16_interpret_ops)
> DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew32_interpret_ops)
> DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_eew64_interpret_ops)
> +DEF_RVV_FUNCTION (vreinterpret, misc, none_preds, iu_v_bool1_interpret_ops)
> DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x2_ops)
> DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x4_ops)
> DEF_RVV_FUNCTION (vlmul_ext, misc, none_preds, all_v_vlmul_ext_x8_ops)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 5bd36a6524e..977ce6b1831 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -181,6 +181,12 @@ along with GCC; see the file COPYING3. If not see
> #define DEF_RVV_EEW64_INTERPRET_OPS(TYPE, REQUIRE)
> #endif
> +/* Use "DEF_RVV_BOOL1_INTERPRET_OPS" macro include all types for BOOL1
> + vinterpret which will be iterated and registered as intrinsic functions.
> */
> +#ifndef DEF_RVV_BOOL1_INTERPRET_OPS
> +#define DEF_RVV_BOOL1_INTERPRET_OPS(TYPE, REQUIRE)
> +#endif
> +
> /* Use "DEF_RVV_X2_VLMUL_EXT_OPS" macro include all types for X2 VLMUL EXT
> which will be iterated and registered as intrinsic functions. */
> #ifndef DEF_RVV_X2_VLMUL_EXT_OPS
> @@ -665,6 +671,16 @@ DEF_RVV_EEW64_INTERPRET_OPS (vuint32m2_t, 0)
> DEF_RVV_EEW64_INTERPRET_OPS (vuint32m4_t, 0)
> DEF_RVV_EEW64_INTERPRET_OPS (vuint32m8_t, 0)
> +DEF_RVV_BOOL1_INTERPRET_OPS (vint8m1_t, 0)
> +DEF_RVV_BOOL1_INTERPRET_OPS (vint16m1_t, 0)
> +DEF_RVV_BOOL1_INTERPRET_OPS (vint32m1_t, 0)
> +DEF_RVV_BOOL1_INTERPRET_OPS (vint64m1_t, RVV_REQUIRE_ELEN_64)
> +
> +DEF_RVV_BOOL1_INTERPRET_OPS (vuint8m1_t, 0)
> +DEF_RVV_BOOL1_INTERPRET_OPS (vuint16m1_t, 0)
> +DEF_RVV_BOOL1_INTERPRET_OPS (vuint32m1_t, 0)
> +DEF_RVV_BOOL1_INTERPRET_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
> +
> DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf4_t, 0)
> DEF_RVV_X2_VLMUL_EXT_OPS (vint8mf2_t, 0)
> @@ -1052,6 +1068,7 @@ DEF_RVV_TUPLE_OPS (vfloat64m4x2_t,
> RVV_REQUIRE_ELEN_FP_64)
> #undef DEF_RVV_EEW16_INTERPRET_OPS
> #undef DEF_RVV_EEW32_INTERPRET_OPS
> #undef DEF_RVV_EEW64_INTERPRET_OPS
> +#undef DEF_RVV_BOOL1_INTERPRET_OPS
> #undef DEF_RVV_X2_VLMUL_EXT_OPS
> #undef DEF_RVV_X4_VLMUL_EXT_OPS
> #undef DEF_RVV_X8_VLMUL_EXT_OPS
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index 0f56f29f7aa..99622e0aa78 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -324,6 +324,13 @@ static const rvv_type_info eew64_interpret_ops[] = {
> #include "riscv-vector-builtins-types.def"
> {NUM_VECTOR_TYPES, 0}};
> +/* A list of bool1 interpret will be registered for intrinsic functions. */
> +static const rvv_type_info bool1_interpret_ops[] = {
> +#define DEF_RVV_BOOL1_INTERPRET_OPS(TYPE, REQUIRE)
> \
> + {VECTOR_TYPE_##TYPE, REQUIRE},
> +#include "riscv-vector-builtins-types.def"
> + {NUM_VECTOR_TYPES, 0}};
> +
> /* A list of x2 vlmul ext will be registered for intrinsic functions. */
> static const rvv_type_info vlmul_ext_x2_ops[] = {
> #define DEF_RVV_X2_VLMUL_EXT_OPS(TYPE, REQUIRE) {VECTOR_TYPE_##TYPE, REQUIRE},
> @@ -1596,6 +1603,14 @@ static CONSTEXPR const rvv_op_info
> iu_v_eew64_interpret_ops
> rvv_arg_type_info (RVV_BASE_eew64_interpret), /* Return type */
> v_args /* Args */};
> +/* A static operand information for vbool1_t func (vector_type)
> + * function registration. */
> +static CONSTEXPR const rvv_op_info iu_v_bool1_interpret_ops
> + = {bool1_interpret_ops, /* Types */
> + OP_TYPE_v, /* Suffix */
> + rvv_arg_type_info (RVV_BASE_bool1_interpret), /* Return type */
> + v_args /* Args */};
> +
> /* A static operand information for vector_type func (vector_type)
> * function registration. */
> static CONSTEXPR const rvv_op_info all_v_vlmul_ext_x2_ops
> @@ -2282,6 +2297,7 @@ static CONSTEXPR const function_type_info
> function_types[] = {
> DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED,
> \
> DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1,
> \
> EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET,
> \
> + BOOL1_INTERPRET,
> \
> X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT,
> \
> X64_VLMUL_EXT, TUPLE_SUBPART)
> \
> {
> \
> @@ -2319,6 +2335,7 @@ static CONSTEXPR const function_type_info
> function_types[] = {
> VECTOR_TYPE_##EEW16_INTERPRET,
> \
> VECTOR_TYPE_##EEW32_INTERPRET,
> \
> VECTOR_TYPE_##EEW64_INTERPRET,
> \
> + VECTOR_TYPE_##BOOL1_INTERPRET,
> \
> VECTOR_TYPE_##X2_VLMUL_EXT,
> \
> VECTOR_TYPE_##X4_VLMUL_EXT,
> \
> VECTOR_TYPE_##X8_VLMUL_EXT,
> \
> @@ -2620,6 +2637,7 @@ required_extensions_p (enum rvv_base_type type)
> case RVV_BASE_eew16_interpret:
> case RVV_BASE_eew32_interpret:
> case RVV_BASE_eew64_interpret:
> + case RVV_BASE_bool1_interpret:
> case RVV_BASE_vlmul_ext_x2:
> case RVV_BASE_vlmul_ext_x4:
> case RVV_BASE_vlmul_ext_x8:
> diff --git a/gcc/config/riscv/riscv-vector-builtins.def
> b/gcc/config/riscv/riscv-vector-builtins.def
> index 0a387fd1617..b3bf067129e 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.def
> +++ b/gcc/config/riscv/riscv-vector-builtins.def
> @@ -79,6 +79,7 @@ along with GCC; see the file COPYING3. If not see
> DOUBLE_TRUNC_SCALAR, DOUBLE_TRUNC_SIGNED, DOUBLE_TRUNC_UNSIGNED,
> \
> DOUBLE_TRUNC_UNSIGNED_SCALAR, DOUBLE_TRUNC_FLOAT, FLOAT, LMUL1, WLMUL1,
> \
> EEW8_INTERPRET, EEW16_INTERPRET, EEW32_INTERPRET, EEW64_INTERPRET,
> \
> + BOOL1_INTERPRET,
> \
> X2_VLMUL_EXT, X4_VLMUL_EXT, X8_VLMUL_EXT, X16_VLMUL_EXT, X32_VLMUL_EXT,
> \
> X64_VLMUL_EXT, TUPLE_SUBPART)
> #endif
> @@ -634,6 +635,7 @@ DEF_RVV_BASE_TYPE (eew8_interpret, get_vector_type
> (type_idx))
> DEF_RVV_BASE_TYPE (eew16_interpret, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (eew32_interpret, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (eew64_interpret, get_vector_type (type_idx))
> +DEF_RVV_BASE_TYPE (bool1_interpret, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (vlmul_ext_x2, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (vlmul_ext_x4, get_vector_type (type_idx))
> DEF_RVV_BASE_TYPE (vlmul_ext_x8, get_vector_type (type_idx))
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index 328fce8d632..c128c3dedac 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -433,6 +433,16 @@ (define_expand "@vreinterpret<mode>"
> }
> )
> +(define_expand "@vreinterpret<mode>"
> + [(set (match_operand:VB 0 "register_operand")
> + (match_operand 1 "vector_any_register_operand"))]
> + "TARGET_VECTOR"
> + {
> + emit_move_insn (operands[0], gen_lowpart (<MODE>mode, operands[1]));
> + DONE;
> + }
> +)
> +
> (define_expand "@vlmul_extx2<mode>"
> [(set (match_operand:<VLMULX2> 0 "register_operand")
> (subreg:<VLMULX2>
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
> new file mode 100644
> index 00000000000..ff5ef2af1bc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
> @@ -0,0 +1,38 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
> +#include "riscv_vector.h"
> +
> +vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
> + return __riscv_vreinterpret_v_i8m1_b1 (src);
> +}
> +
> +vbool1_t test_vreinterpret_v_i16m1_b1 (vint16m1_t src) {
> + return __riscv_vreinterpret_v_i16m1_b1 (src);
> +}
> +
> +vbool1_t test_vreinterpret_v_i32m1_b1 (vint32m1_t src) {
> + return __riscv_vreinterpret_v_i32m1_b1 (src);
> +}
> +
> +vbool1_t test_vreinterpret_v_i64m1_b1 (vint64m1_t src) {
> + return __riscv_vreinterpret_v_i64m1_b1 (src);
> +}
> +
> +vbool1_t test_vreinterpret_v_u8m1_b1 (vuint8m1_t src) {
> + return __riscv_vreinterpret_v_u8m1_b1 (src);
> +}
> +
> +vbool1_t test_vreinterpret_v_u16m1_b1 (vuint16m1_t src) {
> + return __riscv_vreinterpret_v_u16m1_b1 (src);
> +}
> +
> +vbool1_t test_vreinterpret_v_u32m1_b1 (vuint32m1_t src) {
> + return __riscv_vreinterpret_v_u32m1_b1 (src);
> +}
> +
> +vbool1_t test_vreinterpret_v_u64m1_b1 (vuint64m1_t src) {
> + return __riscv_vreinterpret_v_u64m1_b1 (src);
> +}
> +
> +/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)}
> 8 } } */
> +/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)}
> 8 } } */
> --
> 2.34.1
>
>
