Factorize vrmlaldavhq, vrmlaldavhxq, vrmlsldavhq, vrmlsldavhxq
builtins so that they use the same parameterized names.
2022-10-25 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_VRMLxLDAVxQ, MVE_VRMLxLDAVHxQ_P):
New.
(mve_insn): Add vrmlaldavh, vrmlaldavhx, vrmlsldavh, vrmlsldavhx.
(supf): Add VRMLALDAVHXQ_P_S, VRMLALDAVHXQ_S, VRMLSLDAVHQ_P_S,
VRMLSLDAVHQ_S, VRMLSLDAVHXQ_P_S, VRMLSLDAVHXQ_S.
* config/arm/mve.md (mve_vrmlaldavhxq_sv4si)
(mve_vrmlsldavhq_sv4si, mve_vrmlsldavhxq_sv4si)
(mve_vrmlaldavhq_<supf>v4si): Merge into ...
(@mve_<mve_insn>q_<supf>v4si): ... this.
(mve_vrmlaldavhxq_p_sv4si, mve_vrmlsldavhq_p_sv4si)
(mve_vrmlsldavhxq_p_sv4si, mve_vrmlaldavhq_p_<supf>v4si): Merge
into ...
(@mve_<mve_insn>q_p_<supf>v4si): ... this.
---
gcc/config/arm/iterators.md | 28 +++++++++
gcc/config/arm/mve.md | 117 +++++-------------------------------
2 files changed, 43 insertions(+), 102 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 227ba52aed5..729127d8586 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -741,6 +741,20 @@ (define_int_iterator MVE_VMLxLDAVxQ_P [
VMLSLDAVXQ_P_S
])
+(define_int_iterator MVE_VRMLxLDAVxQ [
+ VRMLALDAVHQ_S VRMLALDAVHQ_U
+ VRMLALDAVHXQ_S
+ VRMLSLDAVHQ_S
+ VRMLSLDAVHXQ_S
+ ])
+
+(define_int_iterator MVE_VRMLxLDAVHxQ_P [
+ VRMLALDAVHQ_P_S VRMLALDAVHQ_P_U
+ VRMLALDAVHXQ_P_S
+ VRMLSLDAVHQ_P_S
+ VRMLSLDAVHXQ_P_S
+ ])
+
(define_int_iterator MVE_MOVN [
VMOVNBQ_S VMOVNBQ_U
VMOVNTQ_S VMOVNTQ_U
@@ -979,6 +993,14 @@ (define_int_attr mve_insn [
(VREV64Q_S "vrev64") (VREV64Q_U "vrev64") (VREV64Q_F "vrev64")
(VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd")
(VRHADDQ_S "vrhadd") (VRHADDQ_U "vrhadd")
+ (VRMLALDAVHQ_P_S "vrmlaldavh") (VRMLALDAVHQ_P_U "vrmlaldavh")
+ (VRMLALDAVHQ_S "vrmlaldavh") (VRMLALDAVHQ_U "vrmlaldavh")
+ (VRMLALDAVHXQ_P_S "vrmlaldavhx")
+ (VRMLALDAVHXQ_S "vrmlaldavhx")
+ (VRMLSLDAVHQ_P_S "vrmlsldavh")
+ (VRMLSLDAVHQ_S "vrmlsldavh")
+ (VRMLSLDAVHXQ_P_S "vrmlsldavhx")
+ (VRMLSLDAVHXQ_S "vrmlsldavhx")
(VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh")
(VRMULHQ_S "vrmulh") (VRMULHQ_U "vrmulh")
(VRNDAQ_F "vrnda") (VRNDAQ_M_F "vrnda")
@@ -2323,6 +2345,12 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VMLALDAVXQ_P_S "s")
(VMLSLDAVQ_P_S "s")
(VMLSLDAVXQ_P_S "s")
+ (VRMLALDAVHXQ_P_S "s")
+ (VRMLALDAVHXQ_S "s")
+ (VRMLSLDAVHQ_P_S "s")
+ (VRMLSLDAVHQ_S "s")
+ (VRMLSLDAVHXQ_P_S "s")
+ (VRMLSLDAVHXQ_S "s")
])
;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 584e6129ea5..e2259aa48e9 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1563,47 +1563,20 @@ (define_insn "mve_vqdmulltq_s<mode>"
])
;;
-;; [vrmlaldavhxq_s])
+;; [vrmlaldavhq_u vrmlaldavhq_s]
+;; [vrmlaldavhxq_s]
+;; [vrmlsldavhq_s]
+;; [vrmlsldavhxq_s]
;;
-(define_insn "mve_vrmlaldavhxq_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
- (match_operand:V4SI 2 "s_register_operand" "w")]
- VRMLALDAVHXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vrmlaldavhx.s32 %Q0, %R0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vrmlsldavhq_s])
-;;
-(define_insn "mve_vrmlsldavhq_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
- (match_operand:V4SI 2 "s_register_operand" "w")]
- VRMLSLDAVHQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vrmlsldavh.s32\t%Q0, %R0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vrmlsldavhxq_s])
-;;
-(define_insn "mve_vrmlsldavhxq_sv4si"
+(define_insn "@mve_<mve_insn>q_<supf>v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:V4SI 2 "s_register_operand" "w")]
- VRMLSLDAVHXQ_S))
+ MVE_VRMLxLDAVxQ))
]
"TARGET_HAVE_MVE"
- "vrmlsldavhx.s32\t%Q0, %R0, %q1, %q2"
+ "<mve_insn>.<supf>32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -1653,21 +1626,6 @@ (define_insn "mve_vmullbq_poly_p<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vrmlaldavhq_u vrmlaldavhq_s])
-;;
-(define_insn "mve_vrmlaldavhq_<supf>v4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
- (match_operand:V4SI 2 "s_register_operand" "w")]
- VRMLALDAVHQ))
- ]
- "TARGET_HAVE_MVE"
- "vrmlaldavh.<supf>32\t%Q0, %R0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vcmpeqq_m_f]
;; [vcmpgeq_m_f]
@@ -2826,18 +2784,21 @@ (define_insn "mve_vrmlaldavhaxq_sv4si"
])
;;
-;; [vrmlaldavhxq_p_s])
+;; [vrmlaldavhq_p_u vrmlaldavhq_p_s]
+;; [vrmlaldavhxq_p_s]
+;; [vrmlsldavhq_p_s]
+;; [vrmlsldavhxq_p_s]
;;
-(define_insn "mve_vrmlaldavhxq_p_sv4si"
+(define_insn "@mve_<mve_insn>q_p_<supf>v4si"
[
(set (match_operand:DI 0 "s_register_operand" "=r")
(unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
(match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VRMLALDAVHXQ_P_S))
+ (match_operand:V4BI 3 "vpr_register_operand" "Up")]
+ MVE_VRMLxLDAVHxQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vrmlaldavhxt.s32 %Q0, %R0, %q1, %q2"
+ "vpst\;<mve_insn>t.<supf>32\t%Q0, %R0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -2857,38 +2818,6 @@ (define_insn "mve_vrmlsldavhaxq_sv4si"
[(set_attr "type" "mve_move")
])
-;;
-;; [vrmlsldavhq_p_s])
-;;
-(define_insn "mve_vrmlsldavhq_p_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VRMLSLDAVHQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrmlsldavht.s32 %Q0, %R0, %q1, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vrmlsldavhxq_p_s])
-;;
-(define_insn "mve_vrmlsldavhxq_p_sv4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VRMLSLDAVHXQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrmlsldavhxt.s32 %Q0, %R0, %q1, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vcvtmq_m_s, vcvtmq_m_u])
;;
@@ -2986,22 +2915,6 @@ (define_insn "mve_vcvtq_m_from_f_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vrmlaldavhq_p_u vrmlaldavhq_p_s])
-;;
-(define_insn "mve_vrmlaldavhq_p_<supf>v4si"
- [
- (set (match_operand:DI 0 "s_register_operand" "=r")
- (unspec:DI [(match_operand:V4SI 1 "s_register_operand" "w")
- (match_operand:V4SI 2 "s_register_operand" "w")
- (match_operand:V4BI 3 "vpr_register_operand" "Up")]
- VRMLALDAVHQ_P))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vrmlaldavht.<supf>32 %Q0, %R0, %q1, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vrmlsldavhaq_s])
;;
--
2.34.1
