Factorize vmaxvq vminvq vmaxavq vminavq so that they use the same
pattern.
2022-09-08 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_VMAXVQ_VMINVQ, MVE_VMAXVQ_VMINVQ_P): New.
(mve_insn): Add vmaxav, vmaxv, vminav, vminv.
(supf): Add VMAXAVQ_S, VMAXAVQ_P_S, VMINAVQ_S, VMINAVQ_P_S.
* config/arm/mve.md (mve_vmaxavq_s<mode>, mve_vmaxvq_<supf><mode>)
(mve_vminavq_s<mode>, mve_vminvq_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmaxavq_p_s<mode>, mve_vmaxvq_p_<supf><mode>)
(mve_vminavq_p_s<mode>, mve_vminvq_p_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 26 ++++++++
gcc/config/arm/mve.md | 115 +++++-------------------------------
2 files changed, 40 insertions(+), 101 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index e82ff0d5d9b..5bb7e2be7c8 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -578,6 +578,20 @@ (define_int_iterator MVE_FP_CREATE_ONLY [
VCREATEQ_F
])
+(define_int_iterator MVE_VMAXVQ_VMINVQ [
+ VMAXAVQ_S
+ VMAXVQ_S VMAXVQ_U
+ VMINAVQ_S
+ VMINVQ_S VMINVQ_U
+ ])
+
+(define_int_iterator MVE_VMAXVQ_VMINVQ_P [
+ VMAXAVQ_P_S
+ VMAXVQ_P_S VMAXVQ_P_U
+ VMINAVQ_P_S
+ VMINVQ_P_S VMINVQ_P_U
+ ])
+
(define_int_iterator MVE_MOVN [
VMOVNBQ_S VMOVNBQ_U
VMOVNTQ_S VMOVNTQ_U
@@ -627,8 +641,16 @@ (define_int_attr mve_insn [
(VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
(VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub")
(VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
+ (VMAXAVQ_P_S "vmaxav")
+ (VMAXAVQ_S "vmaxav")
(VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
+ (VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv")
+ (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv")
+ (VMINAVQ_P_S "vminav")
+ (VMINAVQ_S "vminav")
(VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
+ (VMINVQ_P_S "vminv") (VMINVQ_P_U "vminv")
+ (VMINVQ_S "vminv") (VMINVQ_U "vminv")
(VMLAQ_M_N_S "vmla") (VMLAQ_M_N_U "vmla")
(VMLASQ_M_N_S "vmlas") (VMLASQ_M_N_U "vmlas")
(VMOVNBQ_M_S "vmovnb") (VMOVNBQ_M_U "vmovnb")
@@ -1992,6 +2014,10 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VQMOVUNBQ_S "s")
(VQMOVUNTQ_M_S "s")
(VQMOVUNTQ_S "s")
+ (VMAXAVQ_S "s")
+ (VMAXAVQ_P_S "s")
+ (VMINAVQ_S "s")
+ (VMINAVQ_P_S "s")
])
;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 98728e6f3ef..715e85c9998 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -962,21 +962,6 @@ (define_insn "mve_vmaxaq_s<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vmaxavq_s])
-;;
-(define_insn "mve_vmaxavq_s<mode>"
- [
- (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
- (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VMAXAVQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vmaxav.s%#<V_sz_elem>\t%0, %q2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vmaxq_u, vmaxq_s]
;; [vminq_s, vminq_u]
@@ -994,17 +979,20 @@ (define_insn "mve_<max_min_su_str>q_<max_min_supf><mode>"
;;
-;; [vmaxvq_u, vmaxvq_s])
+;; [vmaxavq_s]
+;; [vmaxvq_u, vmaxvq_s]
+;; [vminavq_s]
+;; [vminvq_u, vminvq_s]
;;
-(define_insn "mve_vmaxvq_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
[
(set (match_operand:<V_elem> 0 "s_register_operand" "=r")
(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")]
- VMAXVQ))
+ MVE_VMAXVQ_VMINVQ))
]
"TARGET_HAVE_MVE"
- "vmaxv.<supf>%#<V_sz_elem>\t%0, %q2"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2"
[(set_attr "type" "mve_move")
])
@@ -1023,36 +1011,6 @@ (define_insn "mve_vminaq_s<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vminavq_s])
-;;
-(define_insn "mve_vminavq_s<mode>"
- [
- (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
- (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VMINAVQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vminav.s%#<V_sz_elem>\t%0, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vminvq_u, vminvq_s])
-;;
-(define_insn "mve_vminvq_<supf><mode>"
- [
- (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
- (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VMINVQ))
- ]
- "TARGET_HAVE_MVE"
- "vminv.<supf>%#<V_sz_elem>\t%0, %q2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vmladavq_u, vmladavq_s])
;;
@@ -2366,34 +2324,21 @@ (define_insn "mve_vmaxaq_m_s<mode>"
(set_attr "length""8")])
;;
-;; [vmaxavq_p_s])
-;;
-(define_insn "mve_vmaxavq_p_s<mode>"
- [
- (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
- (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VMAXAVQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmaxavt.s%#<V_sz_elem> %0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vmaxvq_p_u, vmaxvq_p_s])
+;; [vmaxavq_p_s]
+;; [vmaxvq_p_u, vmaxvq_p_s]
+;; [vminavq_p_s]
+;; [vminvq_p_s, vminvq_p_u]
;;
-(define_insn "mve_vmaxvq_p_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_p_<supf><mode>"
[
(set (match_operand:<V_elem> 0 "s_register_operand" "=r")
(unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VMAXVQ_P))
+ MVE_VMAXVQ_VMINVQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vmaxvt.<supf>%#<V_sz_elem> %0, %q2"
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -2413,38 +2358,6 @@ (define_insn "mve_vminaq_m_s<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vminavq_p_s])
-;;
-(define_insn "mve_vminavq_p_s<mode>"
- [
- (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
- (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VMINAVQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vminavt.s%#<V_sz_elem> %0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vminvq_p_s, vminvq_p_u])
-;;
-(define_insn "mve_vminvq_p_<supf><mode>"
- [
- (set (match_operand:<V_elem> 0 "s_register_operand" "=r")
- (unspec:<V_elem> [(match_operand:<V_elem> 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VMINVQ_P))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vminvt.<supf>%#<V_sz_elem>\t%0, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vmladavaq_u, vmladavaq_s])
;;
--
2.34.1
