Factorize vqshlq and vshlq so that they use the same pattern.
2022-09-08 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_SHIFT_M_R, MVE_SHIFT_M_N)
(MVE_SHIFT_N, MVE_SHIFT_R): New.
(mve_insn): Add vqshl, vshl.
* config/arm/mve.md (mve_vqshlq_n_<supf><mode>)
(mve_vshlq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
(mve_vqshlq_r_<supf><mode>, mve_vshlq_r_<supf><mode>): Merge into
...
(@mve_<mve_insn>q_r_<supf><mode>): ... this.
(mve_vqshlq_m_r_<supf><mode>, mve_vshlq_m_r_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_r_<supf><mode>): ... this.
(mve_vqshlq_m_n_<supf><mode>, mve_vshlq_m_n_<supf><mode>): Merge
into ...
(@mve_<mve_insn>q_m_n_<supf><mode>): ... this.
* config/arm/vec-common.md (mve_vshlq_<supf><mode>): Transform
into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 29 +++++++++++
gcc/config/arm/mve.md | 99 ++++++++----------------------------
gcc/config/arm/vec-common.md | 4 +-
3 files changed, 51 insertions(+), 81 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index e7622fe752a..c53b42a86e9 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -435,6 +435,26 @@ (define_int_iterator MVE_INT_N_BINARY_LOGIC [
VORRQ_N_S VORRQ_N_U
])
+(define_int_iterator MVE_SHIFT_M_R [
+ VQSHLQ_M_R_S VQSHLQ_M_R_U
+ VSHLQ_M_R_S VSHLQ_M_R_U
+ ])
+
+(define_int_iterator MVE_SHIFT_M_N [
+ VQSHLQ_M_N_S VQSHLQ_M_N_U
+ VSHLQ_M_N_S VSHLQ_M_N_U
+ ])
+
+(define_int_iterator MVE_SHIFT_N [
+ VQSHLQ_N_S VQSHLQ_N_U
+ VSHLQ_N_S VSHLQ_N_U
+ ])
+
+(define_int_iterator MVE_SHIFT_R [
+ VQSHLQ_R_S VQSHLQ_R_U
+ VSHLQ_R_S VSHLQ_R_U
+ ])
+
(define_int_iterator MVE_RSHIFT_M_N [
VQRSHLQ_M_N_S VQRSHLQ_M_N_U
VRSHLQ_M_N_S VRSHLQ_M_N_U
@@ -540,7 +560,11 @@ (define_int_attr mve_insn [
(VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl")
(VQRSHLQ_N_S "vqrshl") (VQRSHLQ_N_U "vqrshl")
(VQRSHLQ_S "vqrshl") (VQRSHLQ_U "vqrshl")
+ (VQSHLQ_M_N_S "vqshl") (VQSHLQ_M_N_U "vqshl")
+ (VQSHLQ_M_R_S "vqshl") (VQSHLQ_M_R_U "vqshl")
(VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl")
+ (VQSHLQ_N_S "vqshl") (VQSHLQ_N_U "vqshl")
+ (VQSHLQ_R_S "vqshl") (VQSHLQ_R_U "vqshl")
(VQSHLQ_S "vqshl") (VQSHLQ_U "vqshl")
(VQSUBQ_M_N_S "vqsub") (VQSUBQ_M_N_U "vqsub")
(VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub")
@@ -554,7 +578,12 @@ (define_int_attr mve_insn [
(VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl")
(VRSHLQ_N_S "vrshl") (VRSHLQ_N_U "vrshl")
(VRSHLQ_S "vrshl") (VRSHLQ_U "vrshl")
+ (VSHLQ_M_N_S "vshl") (VSHLQ_M_N_U "vshl")
+ (VSHLQ_M_R_S "vshl") (VSHLQ_M_R_U "vshl")
(VSHLQ_M_S "vshl") (VSHLQ_M_U "vshl")
+ (VSHLQ_N_S "vshl") (VSHLQ_N_U "vshl")
+ (VSHLQ_R_S "vshl") (VSHLQ_R_U "vshl")
+ (VSHLQ_S "vshl") (VSHLQ_U "vshl")
(VSUBQ_M_N_S "vsub") (VSUBQ_M_N_U "vsub") (VSUBQ_M_N_F "vsub")
(VSUBQ_M_S "vsub") (VSUBQ_M_U "vsub") (VSUBQ_M_F "vsub")
(VSUBQ_N_S "vsub") (VSUBQ_N_U "vsub") (VSUBQ_N_F "vsub")
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 0d3343b6e29..fb1076aef73 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1389,32 +1389,34 @@ (define_insn "@mve_<mve_insn>q_n_<supf><mode>"
])
;;
-;; [vqshlq_n_s, vqshlq_n_u])
+;; [vqshlq_n_s, vqshlq_n_u]
+;; [vshlq_n_u, vshlq_n_s]
;;
-(define_insn "mve_vqshlq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:SI 2 "immediate_operand" "i")]
- VQSHLQ_N))
+ MVE_SHIFT_N))
]
"TARGET_HAVE_MVE"
- "vqshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
;;
-;; [vqshlq_r_u, vqshlq_r_s])
+;; [vqshlq_r_u, vqshlq_r_s]
+;; [vshlq_r_s, vshlq_r_u]
;;
-(define_insn "mve_vqshlq_r_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_r_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "r")]
- VQSHLQ_R))
+ MVE_SHIFT_R))
]
"TARGET_HAVE_MVE"
- "vqshl.<supf>%#<V_sz_elem>\t%q0, %2"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
])
@@ -1448,36 +1450,6 @@ (define_insn "mve_vrshrq_n_<supf><mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vshlq_n_u, vshlq_n_s])
-;;
-(define_insn "mve_vshlq_n_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:SI 2 "immediate_operand" "i")]
- VSHLQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vshl.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vshlq_r_s, vshlq_r_u])
-;;
-(define_insn "mve_vshlq_r_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:SI 2 "s_register_operand" "r")]
- VSHLQ_R))
- ]
- "TARGET_HAVE_MVE"
- "vshl.<supf>%#<V_sz_elem>\t%q0, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vabdq_f])
;;
@@ -3101,18 +3073,19 @@ (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
(set_attr "length""8")])
;;
-;; [vqshlq_m_r_u, vqshlq_m_r_s])
+;; [vqshlq_m_r_u, vqshlq_m_r_s]
+;; [vshlq_m_r_u, vshlq_m_r_s]
;;
-(define_insn "mve_vqshlq_m_r_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_r_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:SI 2 "s_register_operand" "r")
(match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VQSHLQ_M_R))
+ MVE_SHIFT_M_R))
]
"TARGET_HAVE_MVE"
- "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %2"
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3132,22 +3105,6 @@ (define_insn "mve_vrev64q_m_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vshlq_m_r_u, vshlq_m_r_s])
-;;
-(define_insn "mve_vshlq_m_r_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:SI 2 "s_register_operand" "r")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VSHLQ_M_R))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vsliq_n_u, vsliq_n_s])
;;
@@ -4881,19 +4838,20 @@ (define_insn "mve_vornq_m_<supf><mode>"
(set_attr "length""8")])
;;
-;; [vqshlq_m_n_s, vqshlq_m_n_u])
+;; [vqshlq_m_n_s, vqshlq_m_n_u]
+;; [vshlq_m_n_s, vshlq_m_n_u]
;;
-(define_insn "mve_vqshlq_m_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:SI 3 "immediate_operand" "i")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VQSHLQ_M_N))
+ MVE_SHIFT_M_N))
]
"TARGET_HAVE_MVE"
- "vpst\;vqshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -4914,23 +4872,6 @@ (define_insn "mve_vrshrq_m_n_<supf><mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vshlq_m_n_s, vshlq_m_n_u])
-;;
-(define_insn "mve_vshlq_m_n_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:SI 3 "immediate_operand" "i")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VSHLQ_M_N))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vshlt.<supf>%#<V_sz_elem>\t%q0, %q2, %3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vshrq_m_n_s, vshrq_m_n_u])
;;
diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index 918338ca5c0..b5fc86fdf28 100644
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -357,14 +357,14 @@ (define_expand "@movmisalign<mode>"
}
})
-(define_insn "mve_vshlq_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
[(set (match_operand:VDQIW 0 "s_register_operand" "=w,w")
(unspec:VDQIW [(match_operand:VDQIW 1 "s_register_operand" "w,w")
(match_operand:VDQIW 2 "imm_lshift_or_reg_neon" "w,Ds")]
VSHLQ))]
"ARM_HAVE_<MODE>_ARITH && !TARGET_REALLY_IWMMXT"
"@
- vshl.<supf>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
+ <mve_insn>.<supf>%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
* return neon_output_shift_immediate (\"vshl\", 'i', &operands[2],
<MODE>mode, VALID_NEON_QREG_MODE (<MODE>mode), true);"
[(set_attr "type" "neon_shift_reg<q>, neon_shift_imm<q>")]
)
--
2.34.1
