> @@ -275,6 +284,9 @@ poly_uint16 riscv_vector_chunks;
> /* The number of bytes in a vector chunk. */
> unsigned riscv_bytes_per_vector_chunk;
>
> +/* Prefer vf for auto-vectorizer. */
> +unsigned riscv_vectorization_factor;
> +
Drop this, we have riscv_autovec_lmul
> /* Index R is the smallest register class that contains register R. */
> const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
> GR_REGS, GR_REGS, GR_REGS, GR_REGS,
> @@ -6363,6 +6375,9 @@ riscv_option_override (void)
>
> /* Convert -march to a chunks count. */
> riscv_vector_chunks = riscv_convert_vector_bits ();
> +
> + if (TARGET_VECTOR)
> + riscv_vectorization_factor = RVV_LMUL1;
Drop this, we have riscv_autovec_lmul
> +/* Implement TARGET_AUTOVECTORIZE_VECTOR_MODES for RVV. */
> +static unsigned int
> +riscv_autovectorize_vector_modes (vector_modes *modes, bool)
> +{
> + if (!TARGET_VECTOR)
> + return 0;
> +
> + if (riscv_vectorization_factor == RVV_LMUL1)
Drop this or check with riscv_autovec_lmul.
> + {
> + modes->safe_push (VNx16QImode);
> + modes->safe_push (VNx8QImode);
> + modes->safe_push (VNx4QImode);
> + modes->safe_push (VNx2QImode);
Modes are not consider different VLEN here,
you could ref this patch[1] to see how to get right mode via get_vector_mode
[1]
https://patchwork.sourceware.org/project/gcc/patch/20230419164214.1032017-3-juzhe.zh...@rivai.ai/
