[PATCH] target: [PR109657] (a ? -1 : 0) | b could be optimized better for aarch64

[Andrew Pinski via Gcc-patches]

There is no canonical form for this case defined. So the aarch64 backend needs
a pattern to match both of these forms.

The forms are:
(set (reg/i:SI 0 x0)
    (if_then_else:SI (eq (reg:CC 66 cc)
            (const_int 0 [0]))
        (reg:SI 97)
        (const_int -1 [0xffffffffffffffff])))
and
(set (reg/i:SI 0 x0)
    (ior:SI (neg:SI (ne:SI (reg:CC 66 cc)
                (const_int 0 [0])))
        (reg:SI 102)))

Currently the aarch64 backend matches the first form so this
patch adds a insn_and_split to match the second form and
convert it to the first form.

OK? Bootstrapped and tested on aarch64-linux-gnu with no regressions

        PR target/109657

gcc/ChangeLog:

        * config/aarch64/aarch64.md (*cmov<mode>_insn_m1): New
        insn_and_split pattern.

gcc/testsuite/ChangeLog:

        * gcc.target/aarch64/csinv-2.c: New test.
---
 gcc/config/aarch64/aarch64.md              | 20 +++++++++++++++++
 gcc/testsuite/gcc.target/aarch64/csinv-2.c | 26 ++++++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/csinv-2.c

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index e1a2b265b20..57fe5601350 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4194,6 +4194,26 @@ (define_insn "*cmovsi_insn_uxtw"
   [(set_attr "type" "csel, csel, csel, csel, csel, mov_imm, mov_imm")]
 )
 
+;; There are two canonical forms for `cmp ? -1 : a`.
+;; This is the second form and is here to help combine.
+;; Support `-(cmp) | a` into `cmp ? -1 : a` to be canonical in the backend.
+(define_insn_and_split "*cmov<mode>_insn_m1"
+  [(set (match_operand:GPI 0 "register_operand" "=r")
+        (ior:GPI
+        (neg:GPI
+         (match_operator:GPI 1 "aarch64_comparison_operator"
+          [(match_operand 2 "cc_register" "") (const_int 0)]))
+        (match_operand 3 "register_operand" "r")))]
+  ""
+  "#"
+  "&& true"
+  [(set (match_dup 0)
+       (if_then_else:GPI (match_dup 1)
+        (const_int -1) (match_dup 3)))]
+  {}
+  [(set_attr "type" "csel")]
+)
+
 (define_insn "*cmovdi_insn_uxtw"
   [(set (match_operand:DI 0 "register_operand" "=r")
        (if_then_else:DI
diff --git a/gcc/testsuite/gcc.target/aarch64/csinv-2.c 
b/gcc/testsuite/gcc.target/aarch64/csinv-2.c
new file mode 100644
index 00000000000..89132acb713
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/csinv-2.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* PR target/109657: (a ? -1 : 0) | b could be better */
+
+/* Both functions should have the same assembly of:
+   cmp     w1, 0
+   csinv   w0, w0, wzr, eq
+
+   We should not get:
+   cmp     w1, 0
+   csetm   w1, ne
+   orr     w0, w1, w0
+ */
+/* { dg-final { scan-assembler-times "csinv\tw\[0-9\]" 2 } } */
+/* { dg-final { scan-assembler-not "csetm\tw\[0-9\]" } } */
+unsigned b(unsigned a, unsigned b)
+{
+  if(b)
+    return -1;
+  return a;
+}
+unsigned b1(unsigned a, unsigned b)
+{
+    unsigned t = b ? -1 : 0;
+    return a | t;
+}
-- 
2.31.1