From: Stam Markianos-Wright <stam.markianos-wri...@arm.com>
These newly updated tests were rewritten by Andrea. Some of them
needed further manual fixing as follows:
* The #shift immediate value not in the check-function-bodies as expected
* Some shifts getting optimised to mov immediates, e.g.
`uqshll (1, 1);` -> movs r0, #2; movs r1, #0
* The ACLE was specifying sub-optimal code: lsr+and instead of ubfx. In
this case the test rewritten from the ACLE had the lsr+and pattern,
but the compiler was able to optimise to ubfx. Hence I've changed the
test to now match on ubfx.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/srshr.c: Update shift value.
* gcc.target/arm/mve/intrinsics/srshrl.c: Update shift value.
* gcc.target/arm/mve/intrinsics/uqshl.c: Update shift value and mov imm.
* gcc.target/arm/mve/intrinsics/uqshll.c: Update shift value and mov
imm.
* gcc.target/arm/mve/intrinsics/urshr.c: Update shift value.
* gcc.target/arm/mve/intrinsics/urshrl.c: Update shift value.
* gcc.target/arm/mve/intrinsics/vadciq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadciq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadciq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadciq_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vadcq_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbciq_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_s32.c: Update to ubfx.
* gcc.target/arm/mve/intrinsics/vsbcq_u32.c: Update to ubfx.
---
gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c | 2 +-
gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c | 5 +++--
gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c | 4 ++--
gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c | 4 ++--
.../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 8 ++------
.../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c | 8 ++------
.../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 8 ++------
.../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 8 ++------
gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 8 ++------
22 files changed, 43 insertions(+), 106 deletions(-)
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
index 94e3f42fd33..734375d58c0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshr.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** srshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** srshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
int32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
index 65f28ccbfde..a91943c38a0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/srshrl.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** srshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
int64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
index b23c9d97ba6..58aa7a61e42 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshl.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** uqshl (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
@@ -24,7 +24,7 @@ foo (uint32_t value)
/*
**foo1:
** ...
-** uqshl (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** movs r0, #2
** ...
*/
uint32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
index 6a3d08eea75..5584544aaf7 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/uqshll.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
@@ -24,7 +24,8 @@ foo (uint64_t value)
/*
**foo1:
** ...
-** uqshll (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** movs r0, #2
+** movs r1, #0
** ...
*/
uint64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
index 23afcb8da4c..ff97bf5c473 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshr.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
@@ -24,7 +24,7 @@ foo (uint32_t value)
/*
**foo1:
** ...
-** urshr (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshr (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint32_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
index 8014371f47f..ff6a69d300f 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/urshrl.c
@@ -12,7 +12,7 @@ extern "C" {
/*
**foo:
** ...
-** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
@@ -24,7 +24,7 @@ foo (uint64_t value)
/*
**foo1:
** ...
-** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #shift(?: @.*|)
+** urshrl (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #1(?: @.*|)
** ...
*/
uint64_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
index b262bf94d39..a6a059a19e9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned
*carry_out, mve_pred
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
index d349caed36a..942111339f0 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
unsigned *carry_out, mve_p
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
index 5166993a355..3b68bb6ac33 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
index 080bd61d238..82228491043 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
index 45e6ff03623..0d4cb779254 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned
*carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
index 54f141b2093..a0ba6825d8c 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
index 06d5bae09da..47f5f22dde9 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
index e2111cfd16a..55a961be217 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
index 66a5c4c9da3..dcbaef1a571 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -43,9 +41,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned
*carry_out, mve_pred
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
index 9306f152cde..08f67f665c1 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c
@@ -20,9 +20,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -43,9 +41,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
unsigned *carry_out, mve_p
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
index 0b5040f0b2a..803246c3235 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -35,9 +33,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
index df211a64daa..22d2b4355bc 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c
@@ -16,9 +16,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -35,9 +33,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry_out)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
index 217cfa7ac21..7a332610c69 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -55,9 +53,7 @@ foo (int32x4_t inactive, int32x4_t a, int32x4_t b, unsigned
*carry, mve_pred16_t
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
index dad04d05d68..60902196502 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c
@@ -26,9 +26,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -55,9 +53,7 @@ foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b,
unsigned *carry, mve_pred1
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
index cd033640bcc..523fa32ee0d 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
@@ -47,9 +45,7 @@ foo (int32x4_t a, int32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
int32x4_t
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
index 6ca0c753b5e..ff720fd2df5 100644
--- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c
@@ -22,9 +22,7 @@ extern "C" {
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
@@ -47,9 +45,7 @@ foo (uint32x4_t a, uint32x4_t b, unsigned *carry)
** ...
** vmrs (?:ip|fp|r[0-9]+), FPSCR_nzcvqc(?: @.*|)
** ...
-** lsr (?:ip|fp|r[0-9]+), #29(?: @.*|)
-** ...
-** and (?:ip|fp|r[0-9]+), #1(?: @.*|)
+** ubfx (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #29, #1(?: @.*|)
** ...
*/
uint32x4_t
--
2.25.1
