This patch fixes whitespace errors introduced with
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616807.html
2023-04-26 Patrick O'Neill <patr...@rivosinc.com>
gcc/ChangeLog:
* config/riscv/riscv.cc: Fix whitespace.
* config/riscv/sync.md: Fix whitespace.
Signed-off-by: Patrick O'Neill <patr...@rivosinc.com>
---
Patch was checked with contrib/check_GNU_style.py
Whitespace changes in this patch are 3 flavors:
* Add space between function name and ()
* Remove space before square bracket[]
* 2 spaces between end of comment and */
---
gcc/config/riscv/riscv.cc | 6 +++---
gcc/config/riscv/sync.md | 40 +++++++++++++++++++--------------------
2 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0f890469d7a..1529855a2b4 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7193,7 +7193,7 @@ riscv_subword_address (rtx mem, rtx *aligned_mem, rtx
*shift, rtx *mask,
emit_move_insn (*mask, gen_rtx_ASHIFT (SImode, *mask,
gen_lowpart (QImode, *shift)));
- emit_move_insn (*not_mask, gen_rtx_NOT(SImode, *mask));
+ emit_move_insn (*not_mask, gen_rtx_NOT (SImode, *mask));
}
/* Leftshift a subword within an SImode register. */
@@ -7206,8 +7206,8 @@ riscv_lshift_subword (machine_mode mode, rtx value, rtx
shift,
emit_move_insn (value_reg, simplify_gen_subreg (SImode, value,
mode, 0));
- emit_move_insn(*shifted_value, gen_rtx_ASHIFT (SImode, value_reg,
- gen_lowpart (QImode, shift)));
+ emit_move_insn (*shifted_value, gen_rtx_ASHIFT (SImode, value_reg,
+ gen_lowpart (QImode, shift)));
}
/* Initialize the GCC target structure. */
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index 83be6431cb6..8e95ce77916 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -49,7 +49,7 @@
;; conservatively emit a full FENCE.
(define_insn "mem_thread_fence_1"
[(set (match_operand:BLK 0 "" "")
- (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))
+ (unspec:BLK[(match_dup 0)] UNSPEC_MEMORY_BARRIER))
(match_operand:SI 1 "const_int_operand" "")] ;; model
""
"fence\tiorw,iorw")
@@ -128,10 +128,10 @@
{
/* We have no QImode/HImode atomics, so form a mask, then use
subword_atomic_fetch_strong_nand to implement a LR/SC version of the
- operation. */
+ operation. */
/* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
- is disabled */
+ is disabled. */
rtx old = gen_reg_rtx (SImode);
rtx mem = operands[1];
@@ -193,10 +193,10 @@
{
/* We have no QImode/HImode atomics, so form a mask, then use
subword_atomic_fetch_strong_<mode> to implement a LR/SC version of the
- operation. */
+ operation. */
/* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
- is disabled */
+ is disabled. */
rtx old = gen_reg_rtx (SImode);
rtx mem = operands[1];
@@ -290,10 +290,10 @@
[(set (match_operand:GPR 0 "register_operand" "=&r")
(match_operand:GPR 1 "memory_operand" "+A"))
(set (match_dup 1)
- (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ")
- (match_operand:GPR 3 "reg_or_0_operand" "rJ")
- (match_operand:SI 4 "const_int_operand") ;; mod_s
- (match_operand:SI 5 "const_int_operand")] ;; mod_f
+ (unspec_volatile:GPR[(match_operand:GPR 2 "reg_or_0_operand" "rJ")
+ (match_operand:GPR 3 "reg_or_0_operand" "rJ")
+ (match_operand:SI 4 "const_int_operand") ;; mod_s
+ (match_operand:SI 5 "const_int_operand")] ;; mod_f
UNSPEC_COMPARE_AND_SWAP))
(clobber (match_scratch:GPR 6 "=&r"))]
"TARGET_ATOMIC"
@@ -367,7 +367,7 @@
{
rtx difference = gen_rtx_MINUS (SImode, val, exp);
compare = gen_reg_rtx (SImode);
- emit_move_insn (compare, difference);
+ emit_move_insn (compare, difference);
}
if (word_mode != SImode)
@@ -393,10 +393,10 @@
{
/* We have no QImode/HImode atomics, so form a mask, then use
subword_atomic_cas_strong<mode> to implement a LR/SC version of the
- operation. */
+ operation. */
/* Logic duplicated in gcc/libgcc/config/riscv/atomic.c for use when inlining
- is disabled */
+ is disabled. */
rtx old = gen_reg_rtx (SImode);
rtx mem = operands[1];
@@ -431,15 +431,15 @@
})
(define_insn "subword_atomic_cas_strong"
- [(set (match_operand:SI 0 "register_operand" "=&r") ;;
old value at mem
- (match_operand:SI 1 "memory_operand" "+A")) ;;
mem location
+ [(set (match_operand:SI 0 "register_operand" "=&r") ;;
old value at mem
+ (match_operand:SI 1 "memory_operand" "+A")) ;;
mem location
(set (match_dup 1)
- (unspec_volatile:SI [(match_operand:SI 2 "reg_or_0_operand" "rJ") ;;
expected value
- (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;;
desired value
+ (unspec_volatile:SI[(match_operand:SI 2 "reg_or_0_operand" "rJ") ;;
expected value
+ (match_operand:SI 3 "reg_or_0_operand" "rJ")] ;;
desired value
UNSPEC_COMPARE_AND_SWAP_SUBWORD))
- (match_operand:SI 4 "register_operand" "rI") ;;
mask
- (match_operand:SI 5 "register_operand" "rI") ;;
not_mask
- (clobber (match_scratch:SI 6 "=&r"))] ;;
tmp_1
+ (match_operand:SI 4 "register_operand" "rI") ;;
mask
+ (match_operand:SI 5 "register_operand" "rI") ;;
not_mask
+ (clobber (match_scratch:SI 6 "=&r"))] ;;
tmp_1
"TARGET_ATOMIC && TARGET_INLINE_SUBWORD_ATOMIC"
{
return "1:\;"
@@ -461,7 +461,7 @@
"TARGET_ATOMIC"
{
/* We have no QImode atomics, so use the address LSBs to form a mask,
- then use an aligned SImode atomic. */
+ then use an aligned SImode atomic. */
rtx result = operands[0];
rtx mem = operands[1];
rtx model = operands[2];
--
2.34.1
