Hi ShiHua: Thanks for your contribution to the zfbfmin extension :)
General comments: - Add zfbfmin to riscv_ext_version_table - Add test case to verify the -march is accepted. - Add testcase to test argument passing. - Add testcase for operations. - Add testcase for compares. > +(define_insn "*movbf_softfloat" > + [(set (match_operand:BF 0 "nonimmediate_operand" "=f, r,r,m,*f,*r") > + (match_operand:BF 1 "move_operand" " f,Gr,m,r,*r,*f"))] > + "!TARGET_ZFHMIN Should be TARGET_ZFBFMIN? > @@ -3192,7 +3192,11 @@ riscv_emit_float_compare (enum rtx_code *code, rtx > *op0, rtx *op1) > else if (GET_MODE (cmp_op0) == HFmode && TARGET_64BIT) \ > emit_insn (gen_f##CMP##_quiethfdi4 (*op0, cmp_op0, cmp_op1)); \ > else if (GET_MODE (cmp_op0) == HFmode) \ > - emit_insn (gen_f##CMP##_quiethfsi4 (*op0, cmp_op0, cmp_op1)); \ > + emit_insn (gen_f##CMP##_quietbfsi4 (*op0, cmp_op0, cmp_op1)); \ > + else if (GET_MODE (cmp_op0) == BFmode && TARGET_64BIT) \ > + emit_insn (gen_f##CMP##_quietbfdi4 (*op0, cmp_op0, cmp_op1)); \ > + else if (GET_MODE (cmp_op0) == BFmode) \ > + emit_insn (gen_f##CMP##_quietbfsi4 (*op0, cmp_op0, cmp_op1)); \ > else \ > gcc_unreachable (); \ > *op1 = const0_rtx; \ Do we really need this? I thought we'll always promote to SF before they compare?
