On Fri, 21 Apr 2023 at 20:45, Prathamesh Kulkarni <prathamesh.kulka...@linaro.org> wrote: > > On Fri, 21 Apr 2023 at 14:47, Richard Sandiford > <richard.sandif...@arm.com> wrote: > > > > Prathamesh Kulkarni <prathamesh.kulka...@linaro.org> writes: > > > Hi, > > > I tested the interleave+zip1 for vector init patch and it segfaulted > > > during bootstrap while trying to build > > > libgfortran/generated/matmul_i2.c. > > > Rebuilding with --enable-checking=rtl showed out of bounds access in > > > aarch64_unzip_vector_init in following hunk: > > > > > > + rtvec vec = rtvec_alloc (n / 2); > > > + for (int i = 0; i < n; i++) > > > + RTVEC_ELT (vec, i) = (even_p) ? XVECEXP (vals, 0, 2 * i) > > > + : XVECEXP (vals, 0, 2 * i + 1); > > > > > > which is incorrect since it allocates n/2 but iterates and stores upto n. > > > The attached patch fixes the issue, which passed bootstrap, however > > > resulted in following fallout during testsuite run: > > > > > > 1] sve/acle/general/dupq_[1-4].c tests fail. > > > For the following test: > > > int32x4_t f(int32_t x) > > > { > > > return (int32x4_t) { x, 1, 2, 3 }; > > > } > > > > > > Code-gen without patch: > > > f: > > > adrp x1, .LC0 > > > ldr q0, [x1, #:lo12:.LC0] > > > ins v0.s[0], w0 > > > ret > > > > > > Code-gen with patch: > > > f: > > > movi v0.2s, 0x2 > > > adrp x1, .LC0 > > > ldr d1, [x1, #:lo12:.LC0] > > > ins v0.s[0], w0 > > > zip1 v0.4s, v0.4s, v1.4s > > > ret > > > > > > It shows, fallback_seq_cost = 20, seq_total_cost = 16 > > > where seq_total_cost determines the cost for interleave+zip1 sequence > > > and fallback_seq_cost is the cost for fallback sequence. > > > Altho it shows lesser cost, I am not sure if the interleave+zip1 > > > sequence is better in this case ? > > > > Debugging the patch, it looks like this is because the fallback sequence > > contains a redundant pseudo-to-pseudo move, which is costed as 1 > > instruction (4 units). The RTL equivalent of the: > > > > movi v0.2s, 0x2 > > ins v0.s[0], w0 > > > > has a similar redundant move, but the cost of that move is subsumed by > > the cost of the other arm (the load from LC0), which is costed as 3 > > instructions (12 units). So we have 12 + 4 for the parallel version > > (correct) but 12 + 4 + 4 for the serial version (one instruction too > > many). > > > > The reason we have redundant moves is that the expansion code uses > > copy_to_mode_reg to force a value into a register. This creates a > > new pseudo even if the original value was already a register. > > Using force_reg removes the moves and makes the test pass. > > > > So I think the first step is to use force_reg instead of > > copy_to_mode_reg in aarch64_simd_dup_constant and > > aarch64_expand_vector_init (as a preparatory patch). > Thanks for the clarification! > > > > > 2] sve/acle/general/dupq_[5-6].c tests fail: > > > int32x4_t f(int32_t x0, int32_t x1, int32_t x2, int32_t x3) > > > { > > > return (int32x4_t) { x0, x1, x2, x3 }; > > > } > > > > > > code-gen without patch: > > > f: > > > fmov s0, w0 > > > ins v0.s[1], w1 > > > ins v0.s[2], w2 > > > ins v0.s[3], w3 > > > ret > > > > > > code-gen with patch: > > > f: > > > fmov s0, w0 > > > fmov s1, w1 > > > ins v0.s[1], w2 > > > ins v1.s[1], w3 > > > zip1 v0.4s, v0.4s, v1.4s > > > ret > > > > > > It shows fallback_seq_cost = 28, seq_total_cost = 16 > > > > The zip verson still wins after the fix above, but by a lesser amount. > > It seems like a borderline case. > > > > > > > > 3] aarch64/ldp_stp_16.c's cons2_8_float test fails. > > > Test case: > > > void cons2_8_float(float *x, float val0, float val1) > > > { > > > #pragma GCC unroll(8) > > > for (int i = 0; i < 8 * 2; i += 2) { > > > x[i + 0] = val0; > > > x[i + 1] = val1; > > > } > > > } > > > > > > which is lowered to: > > > void cons2_8_float (float * x, float val0, float val1) > > > { > > > vector(4) float _86; > > > > > > <bb 2> [local count: 119292720]: > > > _86 = {val0_11(D), val1_13(D), val0_11(D), val1_13(D)}; > > > MEM <vector(4) float> [(float *)x_10(D)] = _86; > > > MEM <vector(4) float> [(float *)x_10(D) + 16B] = _86; > > > MEM <vector(4) float> [(float *)x_10(D) + 32B] = _86; > > > MEM <vector(4) float> [(float *)x_10(D) + 48B] = _86; > > > return; > > > } > > > > > > code-gen without patch: > > > cons2_8_float: > > > dup v0.4s, v0.s[0] > > > ins v0.s[1], v1.s[0] > > > ins v0.s[3], v1.s[0] > > > stp q0, q0, [x0] > > > stp q0, q0, [x0, 32] > > > ret > > > > > > code-gen with patch: > > > cons2_8_float: > > > dup v1.2s, v1.s[0] > > > dup v0.2s, v0.s[0] > > > zip1 v0.4s, v0.4s, v1.4s > > > stp q0, q0, [x0] > > > stp q0, q0, [x0, 32] > > > ret > > > > > > It shows fallback_seq_cost = 28, seq_total_cost = 16 > > > > > > I think the test fails because it doesn't match: > > > ** dup v([0-9]+)\.4s, .* > > > > > > Shall it be OK to amend the test assuming code-gen with patch is better ? > > > > Yeah, the new code seems like an improvement. > > > > > 4] aarch64/pr109072_1.c s32x4_3 test fails: > > > For the following test: > > > int32x4_t s32x4_3 (int32_t x, int32_t y) > > > { > > > int32_t arr[] = { x, y, y, y }; > > > return vld1q_s32 (arr); > > > } > > > > > > code-gen without patch: > > > s32x4_3: > > > dup v0.4s, w1 > > > ins v0.s[0], w0 > > > ret > > > > > > code-gen with patch: > > > s32x4_3: > > > fmov s1, w1 > > > fmov s0, w0 > > > ins v0.s[1], v1.s[0] > > > dup v1.2s, v1.s[0] > > > zip1 v0.4s, v0.4s, v1.4s > > > ret > > > > > > It shows fallback_seq_cost = 20, seq_total_cost = 16 > > > I am not sure how interleave+zip1 cost is lesser than fallback seq > > > cost for this case. > > > I assume that the fallback sequence is better here ? > > > > The fix for 1] works for this case too. > Indeed, I verified using force_reg fixes the issues. > I will send a follow up patch after the preparatory patch using force_reg. The attached patch adjusts ldp_stp_16.c, and dupq_[5-6.c] to scan for new code-gen. It passes bootstrap with no regressions reported for testsuite results. For the adjusted tests, it reports "old tests that pass have disappeared", which I assume is OK since they now scan for new code-gen ? Does the patch look OK to commit ?
Thanks, Prathamesh > > Thanks, > Prathamesh > > > > Thanks, > > Richard
[aarch64] Recursively intialize even and odd sub-parts and merge with zip1. gcc/ChangeLog: * config/aarch64/aarch64.cc (aarch64_expand_vector_init_fallback): Rename aarch64_expand_vector_init to this, and remove interleaving case. Recursively call aarch64_expand_vector_init_fallback, instead of aarch64_expand_vector_init. (aarch64_unzip_vector_init): New function. (aarch64_expand_vector_init): Likewise. gcc/testsuite/ChangeLog: * gcc.target/aarch64/ldp_stp_16.c (cons2_8_float): Adjust for new code-gen. * gcc.target/aarch64/sve/acle/general/dupq_5.c: Likewise. * gcc.target/aarch64/sve/acle/general/dupq_6.c: Likewise. * gcc.target/aarch64/vec-init-18.c: Rename interleave-init-1.c to this. * gcc.target/aarch64/vec-init-19.c: New test. * gcc.target/aarch64/vec-init-20.c: Likewise. * gcc.target/aarch64/vec-init-21.c: Likewise. * gcc.target/aarch64/vec-init-22-size.c: Likewise. * gcc.target/aarch64/vec-init-22-speed.c: Likewise. * gcc.target/aarch64/vec-init-22.h: New header. diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index d7e895f8d34..416e062829c 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -22026,11 +22026,12 @@ aarch64_simd_make_constant (rtx vals) return NULL_RTX; } -/* Expand a vector initialisation sequence, such that TARGET is - initialised to contain VALS. */ +/* A subroutine of aarch64_expand_vector_init, with the same interface. + The caller has already tried a divide-and-conquer approach, so do + not consider that case here. */ void -aarch64_expand_vector_init (rtx target, rtx vals) +aarch64_expand_vector_init_fallback (rtx target, rtx vals) { machine_mode mode = GET_MODE (target); scalar_mode inner_mode = GET_MODE_INNER (mode); @@ -22090,38 +22091,6 @@ aarch64_expand_vector_init (rtx target, rtx vals) return; } - /* Check for interleaving case. - For eg if initializer is (int16x8_t) {x, y, x, y, x, y, x, y}. - Generate following code: - dup v0.h, x - dup v1.h, y - zip1 v0.h, v0.h, v1.h - for "large enough" initializer. */ - - if (n_elts >= 8) - { - int i; - for (i = 2; i < n_elts; i++) - if (!rtx_equal_p (XVECEXP (vals, 0, i), XVECEXP (vals, 0, i % 2))) - break; - - if (i == n_elts) - { - machine_mode mode = GET_MODE (target); - rtx dest[2]; - - for (int i = 0; i < 2; i++) - { - rtx x = expand_vector_broadcast (mode, XVECEXP (vals, 0, i)); - dest[i] = force_reg (mode, x); - } - - rtvec v = gen_rtvec (2, dest[0], dest[1]); - emit_set_insn (target, gen_rtx_UNSPEC (mode, v, UNSPEC_ZIP1)); - return; - } - } - enum insn_code icode = optab_handler (vec_set_optab, mode); gcc_assert (icode != CODE_FOR_nothing); @@ -22243,7 +22212,7 @@ aarch64_expand_vector_init (rtx target, rtx vals) } XVECEXP (copy, 0, i) = subst; } - aarch64_expand_vector_init (target, copy); + aarch64_expand_vector_init_fallback (target, copy); } /* Insert the variable lanes directly. */ @@ -22257,6 +22226,81 @@ aarch64_expand_vector_init (rtx target, rtx vals) } } +/* Return even or odd half of VALS depending on EVEN_P. */ + +static rtx +aarch64_unzip_vector_init (machine_mode mode, rtx vals, bool even_p) +{ + int n = XVECLEN (vals, 0); + machine_mode new_mode + = aarch64_simd_container_mode (GET_MODE_INNER (mode), + GET_MODE_BITSIZE (mode).to_constant () / 2); + rtvec vec = rtvec_alloc (n / 2); + for (int i = 0; i < n/2; i++) + RTVEC_ELT (vec, i) = (even_p) ? XVECEXP (vals, 0, 2 * i) + : XVECEXP (vals, 0, 2 * i + 1); + return gen_rtx_PARALLEL (new_mode, vec); +} + +/* Expand a vector initialisation sequence, such that TARGET is + initialized to contain VALS. */ + +void +aarch64_expand_vector_init (rtx target, rtx vals) +{ + /* Try decomposing the initializer into even and odd halves and + then ZIP them together. Use the resulting sequence if it is + strictly cheaper than loading VALS directly. + + Prefer the fallback sequence in the event of a tie, since it + will tend to use fewer registers. */ + + machine_mode mode = GET_MODE (target); + int n_elts = XVECLEN (vals, 0); + + if (n_elts < 4 + || maybe_ne (GET_MODE_BITSIZE (mode), 128)) + { + aarch64_expand_vector_init_fallback (target, vals); + return; + } + + start_sequence (); + rtx halves[2]; + unsigned costs[2]; + for (int i = 0; i < 2; i++) + { + start_sequence (); + rtx new_vals + = aarch64_unzip_vector_init (mode, vals, (i % 2) == 0); + rtx tmp_reg = gen_reg_rtx (GET_MODE (new_vals)); + aarch64_expand_vector_init (tmp_reg, new_vals); + halves[i] = gen_rtx_SUBREG (mode, tmp_reg, 0); + rtx_insn *rec_seq = get_insns (); + end_sequence (); + costs[i] = seq_cost (rec_seq, !optimize_size); + emit_insn (rec_seq); + } + + rtvec v = gen_rtvec (2, halves[0], halves[1]); + rtx_insn *zip1_insn + = emit_set_insn (target, gen_rtx_UNSPEC (mode, v, UNSPEC_ZIP1)); + unsigned seq_total_cost + = (!optimize_size) ? std::max (costs[0], costs[1]) : costs[0] + costs[1]; + seq_total_cost += insn_cost (zip1_insn, !optimize_size); + + rtx_insn *seq = get_insns (); + end_sequence (); + + start_sequence (); + aarch64_expand_vector_init_fallback (target, vals); + rtx_insn *fallback_seq = get_insns (); + unsigned fallback_seq_cost = seq_cost (fallback_seq, !optimize_size); + end_sequence (); + + emit_insn (seq_total_cost < fallback_seq_cost ? seq : fallback_seq); +} + /* Emit RTL corresponding to: insr TARGET, ELEM. */ diff --git a/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c b/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c index 8ab117c4dcd..30c86018773 100644 --- a/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c +++ b/gcc/testsuite/gcc.target/aarch64/ldp_stp_16.c @@ -96,10 +96,10 @@ CONS2_FN (4, float); /* ** cons2_8_float: -** dup v([0-9]+)\.4s, .* +** dup v([0-9]+)\.2s, v1.s\[0\] ** ... -** stp q\1, q\1, \[x0\] -** stp q\1, q\1, \[x0, #?32\] +** stp q0, q0, \[x0\] +** stp q0, q0, \[x0, #?32\] ** ret */ CONS2_FN (8, float); diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_5.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_5.c index 53426c9af5a..c7d6f3ff390 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_5.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_5.c @@ -11,7 +11,7 @@ dupq (int x1, int x2, int x3, int x4) /* { dg-final { scan-assembler-not {\tldr\t} } } */ /* { dg-final { scan-assembler {, [wx]0\n} } } */ -/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[1\], w1\n} } } */ -/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[2\], w2\n} } } */ -/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[3\], w3\n} } } */ +/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[1\], w2\n} } } */ +/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[1\], w3\n} } } */ +/* { dg-final { scan-assembler {\tzip1\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]\.4s\n} } } */ /* { dg-final { scan-assembler {\tdup\tz[0-9]+\.q, z[0-9]+\.q\[0\]\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_6.c b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_6.c index dfce5e7a12a..4745a3815b0 100644 --- a/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_6.c +++ b/gcc/testsuite/gcc.target/aarch64/sve/acle/general/dupq_6.c @@ -12,7 +12,7 @@ dupq (int x1, int x2, int x3, int x4) /* { dg-final { scan-assembler-not {\tldr\t} } } */ /* { dg-final { scan-assembler {, [wx]0\n} } } */ -/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[1\], w1\n} } } */ -/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[2\], w2\n} } } */ -/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[3\], w3\n} } } */ +/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[1\], w2\n} } } */ +/* { dg-final { scan-assembler {\tins\tv[0-9]+\.s\[1\], w3\n} } } */ +/* { dg-final { scan-assembler {\tzip1\tv[0-9]+\.4s, v[0-9]+\.4s, v[0-9]\.4s\n} } } */ /* { dg-final { scan-assembler {\tdup\tz[0-9]+\.q, z[0-9]+\.q\[0\]\n} } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/interleave-init-1.c b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c similarity index 82% rename from gcc/testsuite/gcc.target/aarch64/interleave-init-1.c rename to gcc/testsuite/gcc.target/aarch64/vec-init-18.c index ee775048589..e812d3946de 100644 --- a/gcc/testsuite/gcc.target/aarch64/interleave-init-1.c +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-18.c @@ -7,8 +7,8 @@ /* ** foo: ** ... -** dup v[0-9]+\.8h, w[0-9]+ -** dup v[0-9]+\.8h, w[0-9]+ +** dup v[0-9]+\.4h, w[0-9]+ +** dup v[0-9]+\.4h, w[0-9]+ ** zip1 v[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h ** ... ** ret @@ -23,8 +23,8 @@ int16x8_t foo(int16_t x, int y) /* ** foo2: ** ... -** dup v[0-9]+\.8h, w[0-9]+ -** movi v[0-9]+\.8h, 0x1 +** dup v[0-9]+\.4h, w[0-9]+ +** movi v[0-9]+\.4h, 0x1 ** zip1 v[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h ** ... ** ret diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-19.c b/gcc/testsuite/gcc.target/aarch64/vec-init-19.c new file mode 100644 index 00000000000..e28fdcda29d --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-19.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <arm_neon.h> + +/* +** f_s8: +** ... +** dup v[0-9]+\.8b, w[0-9]+ +** adrp x[0-9]+, \.LC[0-9]+ +** ldr d[0-9]+, \[x[0-9]+, #:lo12:.LC[0-9]+\] +** zip1 v[0-9]+\.16b, v[0-9]+\.16b, v[0-9]+\.16b +** ret +*/ + +int8x16_t f_s8(int8_t x) +{ + return (int8x16_t) { x, 1, x, 2, x, 3, x, 4, + x, 5, x, 6, x, 7, x, 8 }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-20.c b/gcc/testsuite/gcc.target/aarch64/vec-init-20.c new file mode 100644 index 00000000000..9366ca349b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-20.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <arm_neon.h> + +/* +** f_s8: +** ... +** adrp x[0-9]+, \.LC[0-9]+ +** dup v[0-9]+\.8b, w[0-9]+ +** ldr d[0-9]+, \[x[0-9]+, #:lo12:\.LC[0-9]+\] +** ins v0\.b\[0\], w0 +** zip1 v[0-9]+\.16b, v[0-9]+\.16b, v[0-9]+\.16b +** ret +*/ + +int8x16_t f_s8(int8_t x, int8_t y) +{ + return (int8x16_t) { x, y, 1, y, 2, y, 3, y, + 4, y, 5, y, 6, y, 7, y }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-21.c b/gcc/testsuite/gcc.target/aarch64/vec-init-21.c new file mode 100644 index 00000000000..e16459486d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-21.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#include <arm_neon.h> + +/* +** f_s8: +** ... +** adrp x[0-9]+, \.LC[0-9]+ +** ldr q[0-9]+, \[x[0-9]+, #:lo12:\.LC[0-9]+\] +** ins v0\.b\[0\], w0 +** ins v0\.b\[1\], w1 +** ... +** ret +*/ + +int8x16_t f_s8(int8_t x, int8_t y) +{ + return (int8x16_t) { x, y, 1, 2, 3, 4, 5, 6, + 7, 8, 9, 10, 11, 12, 13, 14 }; +} diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-22-size.c b/gcc/testsuite/gcc.target/aarch64/vec-init-22-size.c new file mode 100644 index 00000000000..8f35854c008 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-22-size.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-Os" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Verify that fallback code-sequence is chosen over + recursively generated code-sequence merged with zip1. */ + +/* +** f_s16: +** ... +** sxth w0, w0 +** fmov s0, w0 +** ins v0\.h\[1\], w1 +** ins v0\.h\[2\], w2 +** ins v0\.h\[3\], w3 +** ins v0\.h\[4\], w4 +** ins v0\.h\[5\], w5 +** ins v0\.h\[6\], w6 +** ins v0\.h\[7\], w7 +** ... +** ret +*/ + +#include "vec-init-22.h" diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c b/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c new file mode 100644 index 00000000000..172d56ffdf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-22-speed.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +/* Verify that we recursively generate code for even and odd halves + instead of fallback code. This is so despite the longer code-gen + because it has fewer dependencies and thus has lesser cost. */ + +/* +** f_s16: +** ... +** sxth w0, w0 +** sxth w1, w1 +** fmov d0, x0 +** fmov d1, x1 +** ins v[0-9]+\.h\[1\], w2 +** ins v[0-9]+\.h\[1\], w3 +** ins v[0-9]+\.h\[2\], w4 +** ins v[0-9]+\.h\[2\], w5 +** ins v[0-9]+\.h\[3\], w6 +** ins v[0-9]+\.h\[3\], w7 +** zip1 v[0-9]+\.8h, v[0-9]+\.8h, v[0-9]+\.8h +** ... +** ret +*/ + +#include "vec-init-22.h" diff --git a/gcc/testsuite/gcc.target/aarch64/vec-init-22.h b/gcc/testsuite/gcc.target/aarch64/vec-init-22.h new file mode 100644 index 00000000000..15b889d4097 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vec-init-22.h @@ -0,0 +1,7 @@ +#include <arm_neon.h> + +int16x8_t f_s16 (int16_t x0, int16_t x1, int16_t x2, int16_t x3, + int16_t x4, int16_t x5, int16_t x6, int16_t x7) +{ + return (int16x8_t) { x0, x1, x2, x3, x4, x5, x6, x7 }; +}