On 2/10/23 15:41, Philipp Tomsich wrote:
The vendor-defined XVentanaCondOps extension adds two instructions with semantics identical to Zicond. This plugs the 2 new instruction in using the canonical RTX, which also matches the combiner-input for noce_try_store_flag_mask and noce_try_store_flag, defined for conditional-zero. For documentation on XVentanaCondOps, refer to: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for conditional zero as a single instruction for TARGET_XVENTANACONDOPS. * config/riscv/riscv.md: Include xventanacondops.md. * config/riscv/zicond.md: Enable splitters for TARGET_XVENTANACONDOPS. * config/riscv/xventanacondops.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-and-01.c: New test. * gcc.target/riscv/xventanacondops-and-02.c: New test. * gcc.target/riscv/xventanacondops-eq-01.c: New test. * gcc.target/riscv/xventanacondops-eq-02.c: New test. * gcc.target/riscv/xventanacondops-ifconv-imm.c: New test. * gcc.target/riscv/xventanacondops-le-01.c: New test. * gcc.target/riscv/xventanacondops-le-02.c: New test. * gcc.target/riscv/xventanacondops-lt-01.c: New test. * gcc.target/riscv/xventanacondops-lt-03.c: New test. * gcc.target/riscv/xventanacondops-ne-01.c: New test. * gcc.target/riscv/xventanacondops-ne-03.c: New test. * gcc.target/riscv/xventanacondops-ne-04.c: New test. * gcc.target/riscv/xventanacondops-xor-01.c: New test.
OK with the change to use if-then-else. jeff
